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US 9,319,039 B2Granted
Forwarded clock jitter reduction
AssigneeIntel Corporation
InventorsEduard Roytman, Mahalingam Nagarajan, Pradeep R. Vempada
Life of this patent
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Abstract
In some embodiments, a differential amplifier with duty cycle correction is provided.
Claims15
A chip, comprising:
- a differential amplifier to receive a differential clock;
- and
- an offset compensation circuit coupled to the differential amplifier to adjust offset in the differential clock, the offset compensation circuit to be digitally controlled based on offset in the differential clock, wherein the offset compensation circuit is part of an active high-pass filter circuit.
A chip, comprising:
- a differential amplifier having an input to receive a differential clock and an output to provide a duty cycle adjusted clock;
- and
- an offset adjustment circuit coupled between the input and output, said offset adjustment circuit including a variable offset comparator (VOC) with self offset correction, a differential offset compensation (DOC) circuit having an output coupled to the input of the differential amplifier, and a control circuit coupled between the VOC and DOC to control output clock duty cycle.
Dependencies are inferred from the claim text.