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US 9,319,038 B2Granted
Glitch free input transition detector
AssigneeIntegrated Silicon Solution, Inc.
InventorSeong Jun Jang
Life of this patent
Estimating the term…
Abstract
A circuit for detecting a signal transition on an input signal includes a mirror delay circuit and an input blocking circuit to prevent signal glitches or undesired signal pulses from being passed to the output signal node, thereby preventing signal distortions from being detected as a valid signal transition. The input transition detection circuit generates stable and correct transition detection pulses having a consistent pulse width.
Claims15
A circuit for detecting a signal transition on an input signal, the circuit comprising:
- an input signal path configured to receive the input signal on an input node and to provide a buffered input signal to an output node as an output signal;
- an input transition detector configured to receive the output signal and to generate a transition detection output signal, the transition detection output signal comprising one or more signal pulses that are asserted in response to a signal transition detected on the output signal;
- a mirror delay circuit configured to receive a first signal indicative of the input signal and a second signal being a delayed signal of the first signal, the mirror delay circuit further configured to generate a third signal as a function of the first signal and the second signal, the third signal being asserted in response to the first signal and the second signal having the same logical state and being deasserted in response to the first signal and the second signal having different logical states;
- an input blocking circuit configured to receive the third signal and the transition detection output signal and to generate a switch control signal as a function of the third signal and the transition detection output signal, the switch control signal being asserted in response to the third signal being asserted and the transition detection output signal being deasserted, and the switch control signal being deasserted in response to the third signal being deasserted or the transition detection output signal being asserted;
- and
- the input blocking circuit comprising a switch coupled to the input signal path and controlled by the switch control signal, the switch being open in response to the switch control signal being deasserted to block a signal transition on the input signal to be passed to the output node on the input signal path, and the switch being closed in response to the switch control signal being asserted to pass a signal transition on the input signal to the output node on the input signal path.
3 more elements
A method for detecting a signal transition on an input signal, the method comprising:
- coupling the input signal though an input signal path to an output signal node as an output signal;
- generating a transition detection output signal having one or more detection pulses that are asserted in response to a signal transition detected on the output signal;
- receiving an input signal transition on the input signal;
- blocking input signal path;
- generating a second signal being a delayed signal of a first signal related to the input signal;
- continuing to block the input signal path in response to first signal and the second signal having different logical states;
- determining that the transition detection output signal is deasserted after a previous detection pulse;
- and
- enabling the input signal path in response to first signal and the second signal having the same logical state and to the determining that the transition detection output signal is deasserted.
6 more elements
Dependencies are inferred from the claim text.