Self-adjusting clock doubler and integrated circuit clock distribution system using same

A clock distribution system for an integrated circuit comprising:

• a phase locked loop having an input for receiving an external clock signal, and an output for providing a clock input signal;
• a plurality of clock sub-domains each receiving said clock input signal, wherein each of said plurality of clock sub-domains comprise a clock doubler having an input for receiving said clock input signal, and an output for providing a clock output signal, each clock doubler comprising:
• a switched inverter having first and second control inputs for respectively receiving first and second control signals, a signal input for receiving said clock input signal, and an output;
• an exclusive logic circuit having an first input for receiving said clock input signal, a second input coupled to said output of said switched inverter, and an output for providing said clock output signal;
• and
• a control signal generation circuit for providing said first and second control signals in response to said clock output signal.

A method comprising:

• receiving a clock input signal having a first frequency;
• selectively inverting said clock input signal in response to a feedback signal to form a selectively inverted clock signal;
• combining said clock signal with said selectively inverted clock signal using an exclusive logic function to provide a clock output signal at a second frequency double said first frequency;
• and
• generating said feedback signal in response to said clock output signal.