Source synchronous bus signal alignment compensation mechanism
AssigneeVIA Technologies, Inc.
InventorsVanessa S. Canac, James R. Lundberg
Life of this patent
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AssigneeVIA Technologies, Inc.
InventorsVanessa S. Canac, James R. Lundberg
Estimating the term…
An apparatus having a bit lag control element that measures a propagation time beginning with assertion of a first signal and ending with assertion of a second signal, and that generates a first value indicating an adjusted propagation time. The control element includes delay lock control, adjust logic, and a gray encoder. The delay lock control selects one of a plurality of successively delayed versions of the first signal that coincides with the assertion the second signal, and generates a second value on a lag select bus that indicates the propagation time. The adjust logic is coupled to a circuit and to the lag select bus, and adjusts the second value by an amount prescribed by the circuit to yield a third value that is output to an adjusted lag bus. The gray encoder gray encodes the third value to generate the first value on the lag bus.
An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
A method that compensates for misalignment on a synchronous data bus, the method comprising:
Dependencies are inferred from the claim text.