High-speed CMOS ring voltage controlled oscillator with low supply sensitivity
AssigneeThe Regents of the University of California
InventorsMichael M. Green, Xiaoyan Gui
Life of this patent
Estimating the term…
Abstract
High-speed CMOS ring voltage controlled oscillators with low supply sensitivity have been disclosed. According to one embodiment, a CML ring oscillator comprises a CML negative impedance compensation circuit comprising two cross coupled transistors and a resistor connected to the two transistors for resistive biasing and a CML interpolating delay cell connected in parallel with the CML negative impedance compensation. An impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.
Claims9
A current mode logic (CML) ring oscillator comprising:
- a CML negative impedance compensation circuit comprising two cross coupled transistors and a first resistor connected to the two transistors for resistive biasing;
- and
- a CML interpolating delay cell connected in parallel with the CML negative impedance compensation, the CML interpolating delay cell comprising a first differential pair of transistors and a second differential pair of transistors, wherein a first gate of the first differential pair of transistors is coupled to a second resistor, a second gate of the first differential pair of transistors is coupled to a third resistor, a first gate of the second differential pair of transistors is coupled to the second resistor, and a second gate of the second differential pair of transistors is coupled to the third resistor;
- wherein an impedance change of the CML negative impedance compensation due to supply variation counteracts an impedance change of the CML interpolating delay cell.
A method for providing compensation for voltage supply variation, the method comprising:
- supplying voltage to a current mode logic (CML) interpolating delay cell, the CML interpolating delay cell connected in parallel with a CML negative impedance compensation circuit, the CML interpolating delay cell comprising a first differential pair of transistors and a second differential pair of transistors, wherein a first gate of the first differential pair of transistors is coupled to a first resistor, a second gate of the first differential pair of transistors is coupled to a second resistor, a first gate of the second differential pair of transistors is coupled to the first resistor, and a second gate of the second differential pair of transistors is coupled to the second resistor, and
- counteracting an impedance change of the CML negative impedance compensation circuit due to supply variation with an impedance change of the CML interpolating delay cell.
Dependencies are inferred from the claim text.