Integrated circuit failure prediction using clock duty cycle recording and analysis

A method for monitoring and recording duty cycle data of an integrated circuit (IC), comprising:

• generating, in response to a reference clock, a clock output signal having a duty cycle;
• transmitting the clock output signal to a clock grid configured to distribute the clock output signal to a plurality of remote locations;
• measuring the duty cycle of the clock output signal at a one of the remote locations and at a plurality of time intervals;
• generating duty cycle data values for the clock output signal at the plurality of time intervals;
• modifying, based on at least one duty cycle data value, the duty cycle of the clock output signal;
• and
• writing the duty cycle data values to a memory unit, and
• generating a predicted end-of-life (EOL) date of the IC by applying a model to duty cycle data values from the memory unit, and to an adjustment state of the duty cycle controller.

A method for monitoring and recording duty cycle data of an integrated circuit (IC), comprising:

• measuring, at a predetermined interval, and with a duty cycle measurement unit, a duration of a clock output signal at a first level and a duration of the clock output signal at a second level;
• calculating, from the duration of the clock output signal at the first and at the second level of the clock output signal, duty cycle data values, over a time period;
• storing the duty cycle data values in a storage location in a memory unit;
• receiving an end-of-life (EOL) date request from a requesting client;
• applying a model to at least one of the stored duty cycle data values and to an adjustment state of the duty cycle controller, to generate an output;
• comparing the output of the model to at least one predetermined duty cycle failure value;
• calculating, based on the output of the model, a predicted EOL date;
• and
• transmitting the predicted EOL date to the requesting client.