Amplifier circuit, biasing block with output gain compensation thereof, and electronic apparatus
AssigneeAdvanced Semiconductor Engineering, Inc.
InventorsJaw-Ming Ding, Rong-Hsang Ho, Jia-Hong Mou
Life of this patent
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Abstract
An exemplary embodiment of the present disclosure illustrates an amplifier circuit comprising an amplifier block and a biasing block. The amplifier block is used to receive an input signal and amplify the input signal to generate an output signal. The a biasing block coupled to the amplifier block is used to provide biasing voltages to bias the amplifier block, and compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block, wherein the biasing currents are substantially independent to temperature and/or system voltage variation.
Claims16
An amplifier circuit, comprising:
- an amplifier block, configured to receive an input signal, and amplify the input signal to generate an output signal;
- and
- a biasing block, coupled to the amplifier block, configured to provide biasing voltages to bias the amplifier block, and compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block, wherein the biasing current are substantially independent to temperature and/or system voltage variation;
- wherein the biasing block comprises:
- a DC biasing circuit, coupled to the amplifier block, to provide the biasing voltages to bias the amplifier block;
- and
- an output gain compensation circuit, coupled to the amplifier block and the DC biasing circuit, to receive the biasing voltages and a feedback signal related to the output signal, wherein when an input power of the input signal increases to a specific level, the feedback signal indicates the output gain compensation circuit to compensate the output gain of the amplifier block;
- wherein the DC biasing circuit comprises four transistors to form a Wilson current mirror.
A biasing block with output gain compensation for an amplifier circuit, wherein an amplifier block is configured to receive an input signal and amplify the input signal to generate an output signal, and the biasing block comprises:
- a DC biasing circuit, coupled to the amplifier block, to provide biasing voltages to bias the amplifier block;
- and
- an output gain compensation circuit, coupled to the amplifier block and the DC biasing circuit, to receive the biasing voltages and a feedback signal related to the output signal, wherein when an input power of the input signal increases to a specific level, the feedback signal indicates the output gain compensation circuit to compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block;
- and
- wherein the DC biasing circuit comprises four transistors to form a Wilson current mirror.
A biasing block with output gain compensation for an amplifier circuit, wherein an amplifier block is configured to receive an input signal and amplify the input signal to generate an output signal, and
- the biasing block comprises:
- a DC biasing circuit coupled to the amplifier block, to provide biasing voltages to bias the amplifier block;
- and
- an output gain compensation circuit coupled to the amplifier block and the DC biasing circuit, to receive the biasing voltages and a feedback signal related to the output signal, wherein when an input power of the input signal increases to a specific level, the feedback signal indicates the output gain compensation circuit to compensate an output gain of the amplifier block before the output gain of the amplifier block is compressed, so as to extend a P1 dB compression point of the amplifier block;
- wherein the amplifier block comprises:
- an input matching network, formed by a first resistor, a first capacitor, a source inductor, and a gate inductor;
- an output matching network, formed by a first load inductor, a second load inductor, a load resistor, a first load capacitor, and a second load capacitor;
- a first NMOSFET, wherein a gate of the first NMOSFET is configured to receive the input signal through the input matching network and is coupled to the DC biasing circuit through the input matching network, and a source of the first NMOSFET is grounded through the input matching network;
- and
- a second NMOSFET, wherein a source of the second NMOSFET is coupled to a drain of the first NMOSFET, a drain of the second NMOSFET outputs the output signal and is coupled to a system voltage through the output matching network, and a gate of the second NMOSFET is coupled to the DC biasing circuit.
Dependencies are inferred from the claim text.