Back to results
US 9,318,813 B2Granted
Signal processing block for a receiver in wireless communication
AssigneeMaxLinear, Inc.
InventorsDimpesh Patel, Glenn Gulak, Mahdi Shabany
Life of this patent
Estimating the term…
Loading patent…
Loading patent…
AssigneeMaxLinear, Inc.
InventorsDimpesh Patel, Glenn Gulak, Mahdi Shabany
Estimating the term…
A QRD processor for computing input signals in a receiver for wireless communication relies upon a combination of multi-dimensional Givens Rotations, Householder Reflections and conventional two-dimensional (2D) Givens Rotations, for computing the QRD of matrices. The proposed technique integrates the benefits of multi-dimensional annihilation capability of Householder reflections plus the low-complexity nature of the conventional 2D Givens rotations. Such integration increases throughput and reduces the hardware complexity, by first decreasing the number of rotation operations required and then by enabling their parallel execution. A pipelined architecture is presented (290) that uses un-rolled pipelined CORDIC processors (245a to 245d) iteratively to improve throughput and resource utilization, while reducing the gate count.
A method for transforming a first matrix using a computer comprising a pipelined structure including an input stage, a plurality of Coordinate Rotation Digital Computer (CORDIC) processors, and an output stage, the method comprising:
A processor comprising a pipelined structure including an input stage, a plurality of Coordinate Rotation Digital Computer (CORDIC) processors, and an output stage, the processor being configured to:
Dependencies are inferred from the claim text.