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US 9,318,718 B2Granted
Methods and devices for silicon integrated vertically aligned field effect transistors
AssigneeKing Abdullah University of Science and Technology
InventorJingqi Li
Life of this patent
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Abstract
Embodiments of the present disclosure provide for vertically aligned CNTFET, methods of making vertically aligned CNTFET, methods of using vertically aligned CNTFET, and the like.
Claims19
An apparatus comprising:
- a vertical stack including:
- a first electrode comprising silicon,
- a drain electrode comprising a first drain layer consisting of chromium and a second drain layer consisting of gold;
- and
- a dielectric layer consisting of SiNx, wherein X=1 or 2, wherein the dielectric layer is disposed in between the source electrode and the first drain layer, and wherein the dielectric layer contacts the first drain layer;
- a single-walled carbon nanotube adjacent to a sidewall of the stack, wherein at least a portion of the single-walled carbon nanotube is coupled to the source electrode and at least another portion of the single-walled carbon nanotube is coupled to the drain electrode;
- a gate dielectric adjacent to the single-walled carbon nanotube, wherein the gate dielectric comprises a first gate dielectric layer and a second gate dielectric layer;
- and
- a gate electrode adjacent to the gate dielectric, wherein the gate electrode comprises a first gate electrode layer comprising titanium and a second gate electrode layer comprising gold.
6 more elements
A method comprising:
- forming a source electrode on a substrate, the source electrode comprising silicon;
- forming a dielectric layer on the source electrode the dielectric layer consisting of SiNx, wherein X=1 or 2;
- forming a drain electrode on the dielectric layer, wherein forming the drain electrode comprises disposing a first drain layer consisting of chromium on the dielectric layer and disposing a second drain layer consisting of gold on the first drain layer;
- vertically aligning the source electrode, the dielectric layer, and the drain electrode;
- forming a single-walled carbon nanotube on a side wall of individual ones of the source electrode, the dielectric layer, and the drain electrode such that at least a portion of the single-walled carbon nanotube is coupled to the source electrode and at least another portion of the single-walled carbon nanotube coupled to the drain electrode;
- forming a gate dielectric layer adjacent to the single-walled carbon nanotube, wherein forming the gate dielectric layer comprises depositing a first dielectric layer comprising a metal oxide via electron beam evaporation on the single-walled carbon nanotube and depositing a second dielectric layer comprising a metal oxide via atomic layer deposition on the first dielectric layer;
- and
- forming a gate electrode adjacent to the gate dielectric layer, wherein forming the gate electrode comprises depositing a first gate electrode layer comprising of titanium on the gate dielectric layer and depositing a second gate electrode layer comprising gold on the first gate electrode layer.
5 more elements
Dependencies are inferred from the claim text.