Resistive memory cell having a reduced conductive path area

A method of forming an array of cells, comprising:

• forming a bottom electrode layer on a substrate;
• oxidizing a plurality of exposed regions of the bottom electrode layer to form a plurality of oxide regions spaced apart from each other, each oxide region extending laterally from a respective first lateral side to a respective second lateral side;
• removing regions of the bottom electrode layer between adjacent oxide regions, thereby forming a plurality of bottom electrodes, each bottom electrode having a respective oxide region at an upper side of the bottom electrode and at least one pointed tip region adjacent the first lateral side of the respective oxide region and having a shape defined in part by a shape of the first lateral side of the respective oxide region;
• forming an electrolyte layer and a top electrode layer over the plurality of bottom electrodes and respective oxide regions that were formed prior to forming the pointed tip regions of the bottom electrodes;
• removing portions of the electrolyte layer and a top electrode layer to form an electrolyte region and a top electrode on each bottom electrode and respective oxide region, thereby forming an array of cells, each cell including a respective bottom electrode, a respective oxide region, a respective electrolyte region, and a respective top electrode;
• wherein, for each cell, the respective electrolyte region is arranged between the pointed tip region of the respective bottom electrode and the respective top electrode, thereby providing a path for the formation of at least one conductive filament or vacancy chain from the pointed tip region of the respective bottom electrode to the respective top electrode through the respective electrolyte region.