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US 9,318,692 B1Granted
Self-limited crack etch to prevent device shorting
AssigneeInternational Business Machines Corporation
InventorsBrian A. Bryce, Josephine B. Chang, Hiroyuki Miyazoe
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Abstract
A semiconductor device includes a piezoelectric layer interposed between a first metal layer and a hardmask layer. A first trench extends through the hardmask layer, the piezoelectric layer and the first metal layer. A self-limiting second trench extends through the hardmask layer and the piezoelectric layer without reaching the first metal layer.
Claims20
A method of fabricating a semiconductor device, the method comprising:
- forming a starting substrate including a piezoelectric layer interposed between a first metal layer and a hardmask layer;
- performing a patterning process that forms a first pattern in the hardmask having a first size and a second pattern in the hardmask having a second size less than the first size;
- and
- performing an etching process that transfers the first pattern through the first metal layer while the second pattern self-limits at the piezoelectric layer without reaching the first metal layer.
1 more element
A semiconductor device, comprising:
- a piezoelectric layer interposed between a first metal layer and a hardmask layer;
- a first trench extending through the hardmask layer, the piezoelectric layer and the first metal layer;
- and
- a second trench extending through the hardmask layer and the piezoelectric layer without reaching the first metal layer.
1 more element
Dependencies are inferred from the claim text.