Semiconductor device with an SGT and method for manufacturing the same

A method for manufacturing a semiconductor device having a surrounding gate transistor (SGT), the method comprising:

• a semiconductor pillar forming step of forming a semiconductor pillar on a substrate;
• a first impurity region forming step of forming a first impurity region in a lower part of the semiconductor pillar, the first impurity region containing a donor or acceptor impurity;
• a second impurity region forming step of forming a second impurity region in a top portion of the semiconductor pillar, the second impurity region being disposed above the first impurity region, containing a donor or acceptor impurity, and having the same conductivity type as the first impurity region;
• a first insulating layer forming step of forming a first insulating layer so as to surround an outer periphery of the semiconductor pillar between a region where the first impurity region is formed and a region where the second impurity region is formed;
• a first conductor layer forming step of forming a first conductor layer so as to surround an outer periphery of the first insulating layer and forming an electrically conductive or nonconductive first material layer so as to surround an outer periphery of the first conductor layer;
• a second insulating layer forming step of forming a second insulating layer so as to be in contact with upper end surfaces of the first conductor layer and the first material layer and so that an outer peripheral edge of the second insulating layer is substantially aligned with an outer peripheral edge of the first material layer;
• a third insulating layer forming step of forming a third insulating layer so as to cover the substrate and the semiconductor pillar;
• a contact hole forming step of forming a contact hole in the third insulating layer so as to surround the top portion of the semiconductor pillar and to have a bottom portion that is in contact with a surface layer portion of the second insulating layer and so that an outer periphery of the bottom portion is located on the second insulating layer;
• and
• a second conductor layer forming step of forming, in the contact hole, a second conductor layer so as to be in contact with the surface layer portion of the second insulating layer and to be in contact with a side face of the top portion of the semiconductor pillar in which the second impurity region is formed,
• wherein an SGT is formed in which one of the first impurity region and the second impurity region functions as a source and the other functions as a drain,
• a part of the semiconductor pillar between the first impurity region and the second impurity region functions as a channel,
• the first insulating layer functions as a gate insulating layer,
• the first conductor layer functions as a gate conductor layer, and
• the second conductor layer is electrically connected to the second impurity region located in the top portion of the semiconductor pillar.

A method for manufacturing a semiconductor device having a surrounding gate transistor (SGT), the method comprising:

• a semiconductor pillar forming step of forming a semiconductor pillar on a substrate;
• a first impurity region forming step of forming a first impurity region in a lower part of the semiconductor pillar, the first impurity region containing a donor or acceptor impurity;
• a second impurity region forming step of forming a second impurity region in a top portion of the semiconductor pillar, the second impurity region being disposed above the first impurity region, containing a donor or acceptor impurity, and having the same conductivity type as the first impurity region;
• a first insulating layer forming step of forming a first insulating layer so as to surround an outer periphery of the semiconductor pillar between a region where the first impurity region is formed and a region where the second impurity region is formed;
• a first conductor layer forming step of forming a first conductor layer so as to surround an outer periphery of the first insulating layer;
• a second insulating layer forming step of forming a second insulating layer so as to be in contact with an upper end surface of the first conductor layer;
• a third insulating layer forming step of forming a third insulating layer so as to cover the substrate and the semiconductor pillar;
• a contact hole forming step of forming a contact hole in the third insulating layer so as to surround the top portion of the semiconductor pillar and to have a bottom portion that is in contact with a surface layer portion of the second insulating layer and so that an outer periphery of the bottom portion is located on the second insulating layer;
• and
• a second conductor layer forming step of forming, in the contact hole, a second conductor layer so as to be in contact with the surface layer portion of the second insulating layer and to be in contact with a side face of the top portion of the semiconductor pillar in which the second impurity region is formed,
• wherein an SGT is formed in which one of the first impurity region and the second impurity region functions as a source and the other functions as a drain,
• a part of the semiconductor pillar between the first impurity region and the second impurity region functions as a channel,
• the first insulating layer functions as a gate insulating layer,
• the first conductor layer functions as a gate conductor layer, and
• the second conductor layer is electrically connected to the second impurity region located in the top portion of the semiconductor pillar, and
• the method includes, after the first conductor layer forming step, a step of adjusting upper end surfaces of the first conductor layer, the first insulating layer, and the third insulating layer to be at the same height on a side portion of the semiconductor pillar.