Layout configurations for integrating schottky contacts into a power transistor device

A semiconductor device comprising:

• a vertical FET device comprising:
• a substrate;
• a drift layer on the substrate and including a first surface opposite the substrate;
• at least four junction implants, each of the at least four junction implants extending from the first surface of the drift layer towards the substrate and towards a center of the drift layer, wherein the at least four junction implants are separated from one another by a portion of the drift layer;
• a gate oxide layer on the first surface of the drift layer, such that the gate oxide layer partially overlaps and runs between each one of the at least four junction implants;
• a gate contact on the gate oxide layer;
• a plurality of source contacts, each on a different one of the at least four junction implants and separated from the gate oxide layer and the gate contact;
• a drain contact on the substrate opposite the drift layer;
• and
• at least two bypass diodes, each one of the bypass diodes comprising a Schottky metal contact on the first surface of the drift layer, such that each Schottky metal contact runs between two of the at least four junction implants.