US 9,318,577 B2Granted

Semiconductor device and method for manufacturing semiconductor device

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorsJunichi Koezuka, Satoshi Shinohara, Miki Suzuki, Hideto Ohnuma

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Abstract

A semiconductor device is provided, which includes a single crystal semiconductor layer formed over an insulating surface and having a source region, a drain region, and a channel formation region, a gate insulating film covering the single crystal semiconductor layer and a gate electrode overlapping with the channel formation region with the gate insulating film interposed therebetween. In the semiconductor device, at least the drain region of the source and drain regions includes a first impurity region adjacent to the channel formation region and a second impurity region adjacent to the first impurity region. A maximum of an impurity concentration distribution in the first impurity region in a depth direction is closer to the insulating surface than a maximum of an impurity concentration distribution in the second impurity region in a depth direction.

Claims25

Dependent claims

A method for manufacturing a semiconductor device, comprising the steps of:

forming a semiconductor layer over an insulating surface;
forming a gate insulating film over the semiconductor layer, the gate insulating film comprising a first gate insulating portion, a second gate insulating portion and a third gate insulating portion;
forming a first conductive film over the gate insulating film;
forming a second conductive film over the first conductive film;
forming a first mask layer and a second mask layer over the second conductive film by using a light exposure mask configured to transmit light with a plurality of intensities;
forming a first conductive layer overlapping a first region of the semiconductor layer and a second conductive layer over and in contact with the first conductive layer by etching the second conductive film and the first conductive film using the first mask layer, and a third conductive layer overlapping a second region of the semiconductor layer by etching the second conductive film and the first conductive film using the second mask layer;
and
adding an impurity element imparting one conductivity type to both the second region of the semiconductor layer and a third region of the semiconductor layer by using the first conductive layer, the second conductive layer, and the third conductive layer as a mask,
wherein the first region of the semiconductor layer and the first gate insulating portion overlap each other,
wherein the second region of the semiconductor layer and the second gate insulating portion overlap each other,
wherein the third region of the semiconductor layer and the third gate insulating portion overlap each other,
wherein the third gate insulating portion is positioned between the first gate insulating portion and the second gate insulating portion, and
wherein the third gate insulating portion is exposed after forming the third conductive layer.

10 more elements

A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate insulating film over a semiconductor region, the semiconductor region comprising a channel formation region, a first region, and a second region;
forming a first conductive film over the gate insulating film;
forming a second conductive film over the first conductive film;
forming a first mask layer over the second conductive film;
forming a first conductive layer and a second conductive layer over and in contact with the first conductive layer by etching the second conductive film and the first conductive film using the first mask layer;
forming a second mask layer by ashing the first mask layer;
forming a third conductive layer by etching the second conductive layer using the second mask layer;
and
adding an impurity element imparting one conductivity type to both the first region and the second region by using the first conductive layer and the third conductive layer as a mask,
wherein the gate insulating film comprises a first gate insulating portion, a second gate insulating portion and a third gate insulating portion,
wherein the channel formation region and the first gate insulating portion overlap each other,
wherein the first region and the second gate insulating portion overlap each other,
wherein the second region and the third gate insulating portion overlap each other,
wherein the third gate insulating portion is positioned between the first gate insulating portion and the second gate insulating portion, and
wherein the third gate insulating portion is exposed after forming the third conductive layer.

12 more elements

A method for manufacturing a semiconductor device, comprising the steps of:

forming a gate insulating film over a semiconductor region, the semiconductor region comprising a channel formation region, a first region, and a second region;
forming a first conductive film over the gate insulating film;
forming a second conductive film over the first conductive film;
forming a first mask layer over the second conductive film;
forming a first conductive layer and a second conductive layer over and in contact with the first conductive layer by etching the second conductive film and the first conductive film using the first mask layer;
forming a second mask layer by ashing the first mask layer;
forming a third conductive layer by etching the second conductive layer using the second mask layer;
adding an impurity element imparting one conductivity type to both the first region and the second region by using the first conductive layer and the third conductive layer as a mask;
and
forming a fourth conductive layer by etching the first conductive layer using the third conductive layer as a mask,
wherein the gate insulating film comprises a first gate insulating portion, a second gate insulating portion and a third gate insulating portion,
wherein the channel formation region and the first gate insulating portion overlap each other,
wherein the first region and the second gate insulating portion overlap each other,
wherein the second region and the third gate insulating portion overlap each other,
wherein the third gate insulating portion is positioned between the first gate insulating portion and the second gate insulating portion, and
wherein the third gate insulating portion is exposed after forming the third conductive layer.

13 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/284,857Filed 22 May 2014 · division
Priority: JP 2010-28067016 Dec 2010
Published: US 2014/0256096 A111 Sep 2014
Granted: 19 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10D 30/0323
Comprising silicon, e.g. amorphous silicon or polysilicon: comprising monocrystalline silicon
H10D 30/022
Of FETs having insulated gates [IGFET]: having lightly-doped source or drain extensions selectively formed at the sides of the gates
H10D 30/6717
Characterised by the doping profiles, e.g. having lightly-doped source or drain extensions: the source and the drain regions being asymmetrical
H10D 86/0231
Of multiple TFTs: using masks, e.g. half-tone masks

Family

Application13/315,322Parent of this division · filed 9 Dec 2011
US 2014/0256096 A1Pre-grant publication · published 11 Sep 2014
US 8,766,361 B2Parent of this division
US 2012/0153395 A1Published application
US 9,318,577 B2This patent

From the US filing history. Foreign family members aren’t listed.