Unit cells of nonvolatile memory devices, cell arrays of nonvolatile memory devices, and methods of fabricating the same
AssigneeSK hynix Inc.
InventorYoung Joon Kwon
Life of this patent
Estimating the term…
Abstract
Unit cells including a substrate having an active region, a first charge trap pattern disposed on the substrate to intersect the active region, a second charge trap pattern disposed on the substrate to intersect the active region and spaced apart from the first charge trap pattern, a first junction region disposed in the active region between the first and second charge trap patterns, a second junction region disposed in the active region adjacent to one side of the first charge trap pattern opposite to the second charge trap pattern, and a third junction region disposed in the active region adjacent to one side of the second charge trap pattern opposite to the first charge trap pattern.
Claims15
A unit cell of a nonvolatile memory device, the unit cell comprising:
- a substrate having an active region;
- a first charge trap pattern disposed on the substrate to intersect the active region;
- a second charge trap pattern disposed on the substrate to intersect the active region and spaced apart from the first charge trap pattern;
- a first junction region disposed in the active region between the first and second charge trap patterns;
- a second junction region disposed in the active region adjacent to one side of the first charge trap pattern opposite to the second charge trap pattern and spaced apart from the first junction region by a first planar channel region;
- and
- a third junction region disposed in the active region adjacent to one side of the second charge trap pattern opposite to the first charge trap pattern and spaced apart from the first junction region by a second planar channel region,
- wherein the first charge trap pattern includes a first tunneling laver, a first charge trap layer, a first insulation layer and a first control gate layer which are sequentially stacked,
- wherein the first planar channel region between the first junction region and the second junction region is entirely overlapped with the first charge trap layer,
- wherein the second charge trap pattern includes a second tunneling layer, a second charge trap layer, a second insulation layer and a second control gate layer which are sequentially stacked, and
- wherein the second planar channel region between the first junction region and the third junction region is entirely overlapped with the second charge trap layer.
A cell array of a nonvolatile memory device, the cell array comprising:
- a plurality of bit lines extending in a bit line direction;
- a plurality of word lines including odd-numbered word lines and even-numbered word lines that extend in a word line direction intersecting the bit line direction;
- a plurality of source lines extending in the word line direction;
- and
- a plurality of unit cells disposed at intersections of the bit lines and the source lines, respectively,
- wherein each of the unit cells includes a first charge storage transistor and a second charge storage transistor that are connected in series along the bit line direction to share a first junction region,
- wherein each of the first charge storage transistors includes a first control gate layer, the first junction region and a second junction region, and each of the second charge storage transistors includes a second control gate layer, the first junction region and a third junction region,
- wherein the first control gate layer and the second control gate layer of each of the unit cells are electrically connected to one of the odd-numbered word lines and one of the even-numbered word lines, respectively,
- wherein the second junction region and the third junction region of each of the unit cells are electrically connected to one of the bit lines,
- wherein the first junction region of each of the unit cells is electrically connected to one of the source lines.
Dependencies are inferred from the claim text.