Integration of a non-volatile memory (NVM) cell and a logic transistor and method therefor
AssigneeFreescale Semiconductor, Inc.
InventorsAsanga H. Perera, Sung-Taeg Kang
Life of this patent
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Abstract
A method of making a semiconductor device includes forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer. A logic gate structure is formed in a logic region of the semiconductor device. A hard mask is formed over at least the metal electrode portion. The nonvolatile memory region is selectively etched such that a first recess is formed in the first gate and a second recess is formed in the second gate.
Claims16
A method of making a semiconductor device, the method comprising:
- forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate separated from a second gate by a charge storage layer;
- forming a logic gate structure in a logic region of the semiconductor device;
- forming a hard mask over at least the logic gate structure;
- and
- selectively etching the nonvolatile memory region such that a first recess is formed in the first gate and a second recess is formed in the second gate.
A method of making a semiconductor device, the method comprising:
- forming a memory gate structure in a nonvolatile memory region of the semiconductor device, wherein the memory gate structure comprises a first gate structure separated from a second gate structure by a charge storage layer, wherein the first gate structure comprises an electrode portion and a dielectric portion;
- forming a logic gate structure in a logic region of the semiconductor device, wherein the logic gate structure comprises a first dummy portion and a second dummy portion, wherein the logic gate structure is substantially the same height as the first gate structure;
- selectively polishing the nonvolatile memory region and the logic region such that the dielectric portion and the second dummy portion are substantially removed;
- replacing the first dummy portion with a metal gate material;
- forming a hard mask over at least the logic gate structure comprising the metal gate material;
- and
- selectively etching the nonvolatile memory region such that a first recess is formed in the first gate structure and a second recess is formed in the second gate structure.
Dependencies are inferred from the claim text.