Method of fabricating semiconductor device having grooved source contact region

A method of fabricating a semiconductor device, comprising:

• forming a channel layer on a substrate;
• forming trench patterns in the channel layer;
• forming impurity bodies in the channel layer between the trench patterns;
• forming grooves in the impurity bodies formed in the channel layer;
• forming source isolation regions in the impurity bodies at bottom portions of the grooves;
• and
• forming source regions in the impurity bodies at sidewall portions of the grooves,
• wherein the source isolation regions directly contact the source regions on either side of the sidewall portions of the grooves;
• wherein the forming of the trench patterns comprises forming cell trench patterns, and
• the forming of the cell trench patterns comprises:
• forming cell trenches in the channel layer;
• forming cell shield patterns in lower portions of the cell trenches;
• forming cell gate patterns on the cell shield patterns positioned within the cell trenches;
• and
• forming cell capping patterns on the cell gate patterns positioned within the cell trenches;
• wherein the forming of the cell shield patterns comprises:
• conformally forming a preliminary cell shield insulating layer on inner walls of the cell trenches;
• forming a preliminary cell shield electrode on the preliminary cell shield insulating layer to fill the cell trenches;
• recessing the preliminary cell shield electrode to form a cell shield electrode having a top surface disposed in the middle region of the cell trench;
• and
• recessing the preliminary cell shield insulating layer to form a cell shield insulating layer to expose upper portions of the inner walls of the cell trenches and having a top surface disposed at a lower level than the top surface of the cell shield electrode;
• wherein the forming of the cell gate patterns comprises:
• forming a cell gate insulating layer on the top surface of the cell shield electrode and the inner walls of the cell trenches;
• forming a preliminary cell gate electrode on the cell gate insulating layer to fill the cell trenches;
• and
• recessing the preliminary cell gate electrode to form a cell gate electrode having a top surface disposed in the middle of the cell trench;
• and
• wherein the forming of the cell capping pattern comprises:
• forming a cell buffer layer on the top surface of the cell gate electrode;
• forming a cell capping stopper layer on the cell buffer layer and the inner walls of the cell trenches;
• forming a preliminary cell capping layer on the cell capping stopper layer to fill the cell trenches;
• and
• planarizing the preliminary cell capping layer to a cell capping layer, so that the cell capping layer remains only within the cell trenches.