Power semiconductor device with dual field plate arrangement and method of making

A method of making a semiconductor device, comprising:

• providing a substrate;
• forming a gate insulating layer on a surface of the substrate;
• forming a plurality of gate electrodes on the gate insulating layer;
• forming, by chemical vapor deposition, an insulating film overlying the gate electrodes and gate insulating layer;
• annealing the substrate having the gate electrodes and gate insulating layer film formed thereon at a temperature sufficient to increase the dielectric breakdown strength thereof;
• etching source electrode openings, drain electrode openings, and field plate electrode openings partially inwardly of the insulating layer, the field plate electrode opening overlying the gate electrode and extending therefrom in the direction of the drain electrode openings;
• etching the source and the drain electrode openings through a remaining insulating film thickness and the gate insulating layer to the substrate, while simultaneously etching only that portion of the remaining insulating film thickness in the field plate electrode opening at a location which overlies the gate electrode through the remaining insulating film to the gate electrode;
• simultaneously depositing metal into the source, drain, and field plate electrode openings, and over a surface of the remaining insulating film to form a metal layer;
• and
• pattern etching the metal layer overlying the remaining insulating film to isolate source electrodes in the source electrode openings, first field plate electrodes in the field plate electrode openings and drain electrodes in the drain electrode openings from one another.