Methods and systems to reduce location-based variations in switching characteristics of 3D ReRAM arrays

A method for manufacturing a semiconductor memory, comprising:

• depositing a first control line layer over a substrate;
• depositing a memory element layer over the first control line layer;
• depositing an embedded resistor layer over the first control line layer, the embedded resistor layer includes a first portion associated with a first set of embedded resistors and a second portion associated with a second set of embedded resistors, the first set of embedded resistors are embedded within a first set of memory cells, the second set of embedded resistors are embedded within a second set of memory cells, the first set of memory cells are connected to a first set of word lines and a first set of bit lines, the second set of memory cells are connected to a second set of word lines and a second set of bit lines, the first set of word lines are longer than the second set of word lines, the first set of bit lines are longer than the second set of bit line;
• and adjusting the first set of embedded resistors to be less resistive than the second set of embedded resistors, the adjusting the first set of embedded resistors includes performing a selective ion implantation to the first set of embedded resistors.