Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array, the memory cell array comprising a plurality of first wiring lines, a plurality of second wiring lines extending crossing the first wiring lines, and a plurality of memory cells disposed at intersections of the first and second wiring lines, the memory cells being stacked in a direction perpendicular to a substrate, each memory cell comprising a variable resistance element;
• a first select transistor layer comprising a first select transistor operative to select one of the first wiring lines;
• a second select transistor layer comprising a second select transistor operative to select one of the second wiring lines;
• and
• a peripheral circuit layer provided on the substrate, the peripheral circuit layer comprising a peripheral circuit that controls a voltage applied to one of the memory cells,
• the first select transistor layer being provided below the memory cell array in a direction perpendicular to the substrate, and
• the second select transistor layer being provided above the memory cell array in a direction perpendicular to the substrate.