US 9,318,501 B2 · Methods and structures for split gate memory cell scaling with merged control gates

Abstract

A memory device has first and second memory cells in and over a substrate. A first doped region is in a first active region. A top surface of the first active region is substantially coplanar with a top surface of the first doped region. A control gate is over the first doped region and extends over a first side of the first doped region and over a second side of the first doped region. A charge storage layer is between the first control gate and the first active region including between the first select gate and the first doped region. A first select gate is over the first active region on the first side of the first doped region and adjacent to the control gate. A second select gate is over the first active region on the second side of the first doped region and adjacent to the control gate.

Claims11

Dependent claims

A method of making a memory device using a substrate, comprising:

forming a first select gate over the substrate;
forming a second select gate over the substrate;
forming a first doped region in the substrate between the first select gate and the second select gate, wherein a top surface of the first doped region is substantially coplanar with a top surface of the substrate;
forming a control gate over the first doped region, between the first doped region and the first select gate, and between the first doped region and the second select gate;
and
forming a charge storage layer over the substrate including over the first doped region prior to forming the control gate.

3 more elements

Dependencies are inferred from the claim text.

Methods and structures for split gate memory cell scaling with merged control gates

Life of this patent

Methods and structures for split gate memory cell scaling with merged control gates

Life of this patent

Abstract

Claims11