A method of manufacturing a semiconductor device comprising a memory cell of a nonvolatile memory formed in a semiconductor substrate located in a first region, and a MISFET formed in the semiconductor substrate located in a second region,
- the memory cell including a first gate electrode, and a second gate electrode which are formed over the semiconductor substrate to be adjacent to each other, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and a second gate insulating film formed between the second gate electrode and the semiconductor substrate and having a charge storage portion therein,
- the MISFET including a third gate electrode formed over the semiconductor substrate and a third gate insulating film formed between the third gate electrode and the semiconductor substrate,
- the method comprising the steps of:
- (a) providing the semiconductor substrate;
- (b) forming, over the semiconductor substrate located in the first region, the first gate electrode via the first gate insulating film, and the second gate electrode via the second gate insulating film;
- (c) forming, over the semiconductor substrate, a first insulating film so as to cover the first gate electrode and the second gate electrode;
- (d) polishing an upper surface of the first insulating film to planarize the upper surface of the first insulating film;
- (e) after the step (d), forming, over the semiconductor substrate, a first conductive film for the third gate electrode so as to cover the first gate electrode, the second gate electrode, and the first insulating film;
- (f) patterning the first conductive film to form the third gate electrode in the second region;
- and
- (g) after the step (f), removing the first insulating film,
- wherein the step (b) includes the steps of:
- (b1) forming, over a main surface of the semiconductor substrate, a second insulating film for the first gate insulating film;
- (b2) forming, over the second insulating film, a second conductive film for the first gate electrode;
- (b3) patterning the second conductive film to form the first gate electrode in the first region;
- (b4) forming, over the main surface of the semiconductor substrate, a third insulating film for the second gate insulating film so as to cover the first gate electrode;
- (b5) forming, over the third insulating film, a third conductive film for the second gate electrode;
- (b6) etching back the third conductive film to leave the third conductive film over a side wall of the first gate electrode via the third insulating film and thus form the second gate electrode;
- and
- (b7) removing a portion of the third insulating film which is uncovered with the second gate electrode,
- wherein, in the step (b3), the second conductive film is left in the second region,
- wherein, in the step (c), over the semiconductor substrate, the first insulating film is formed so as to cover the first gate electrode and the second gate electrode, each located in the first region, and the second conductive film located in the second region, and
- the method further comprises, after the step (d) and prior to the step (e), the step of:
- (d1) removing the second conductive film from the second region.