Nonvolatile memory devices having single-layered floating gates
AssigneeSK hynix Inc.
InventorTae Ho Lee
Life of this patent
Estimating the term…
Abstract
A nonvolatile memory device includes a plurality of twin cells arrayed on a substrate. Each of the plurality of twin cells includes a drain mesa protruding from a surface of a substrate. A first source and a second source are disposed in the substrate and spaced apart from the drain mesa. A first floating gate overlaps with a first sidewall surface of the drain mesa and extends onto the first source, and a second floating gate overlaps with a second sidewall surface of the drain mesa and extends onto the second source. Related methods are also provided.
Claims17
A nonvolatile memory device comprising:
- a first junction protruding from a surface of a substrate;
- a second junction disposed in the substrate and spaced apart from the first junction;
- and
- a floating gate overlapping a sidewall surface of the first junction to overlap a first impurity region in the sidewall surface of the first junction and extending to the second junction,
- wherein the floating gate extends over a portion of a top surface of the first junction.
A nonvolatile memory device comprising:
- a drain mesa protruding from a surface of a substrate, wherein the drain mesa has first and second sidewall surfaces, wherein each of the first and second sidewall surfaces has a first impurity region;
- a first source and a second source disposed in the substrate and spaced apart from the drain mesa, the first source being adjacent to the first sidewall surface of the drain mesa and the second source being adjacent to the second sidewall surface of the drain mesa opposite to the first sidewall surface;
- a first floating gate overlapping the first sidewall surface of the drain mesa to overlap the first impurity region in the first sidewall surface of the drain mesa and extending to the first source;
- and
- a second floating gate overlapping the second sidewall surface of the drain mesa to overlap the first impurity region in the second sidewall surface of the drain mesa and extending to the second source,
- wherein the first and second floating gates extend over a top surface of the drain mesa.
A nonvolatile memory device comprising:
- a plurality of twin cells arrayed in rows and columns and provided over a substrate, wherein each of the twin cells includes:
- a first source and a second source disposed in the substrate,
- a drain mesa protruding from a surface of the substrate between the first and second sources, wherein the drain mesa has first and second sidewall surfaces, wherein each of the first and second sidewall surfaces has a first impurity region,
- a first floating gate overlapping the first sidewall surface of the drain mesa to overlap the first impurity region in the first sidewall surface of the drain mesa and extending to the first source adjacent to the first sidewall surface of the drain mesa, and a second floating gate overlapping the second sidewall surface of the drain mesa to overlap the first impurity region in the second sidewall surface of the drain mesa and extending to the second source adjacent to the second sidewall surface of the drain mesa;
- first source lines disposed in parallel to the columns, each of the first source lines being coupled to the first sources of the twin cells arranged along the respective columns;
- second source lines disposed in parallel to the columns, each of the second source lines being coupled to the second sources of the twin cells arranged along the respective columns;
- first bit lines disposed in parallel to the rows, each of the first bit lines being coupled to the drain mesas of odd-numbered twin cells arranged in the respective rows;
- and
- second bit lines disposed in parallel to the rows, each of the second bit lines being coupled to the drain mesas of even-numbered twin cells arranged in the respective rows,
- wherein the first and second floating gates extend over a top surface of the drain mesa.
Dependencies are inferred from the claim text.