Semiconductor device including capacitor and double-layer metal contact and fabrication method thereof

A method for fabricating a semiconductor device comprising a capacitor and a double-layer metal contact, the method comprising:

• forming a gate of a peripheral transistor for a peripheral circuit over a peripheral region of a semiconductor substrate including a cell region and the peripheral region;
• forming a first interlayer insulating layer covering the gate;
• forming a first contact and a first peripheral circuit wiring layer pattern, which are connected to the gate so as to constitute the peripheral circuit;
• forming a second interlayer insulating layer over the first interlayer insulating layer to cover the first peripheral circuit wiring layer pattern,
• wherein the second interlayer insulating layer includes a first portion and a second portion, and
• wherein the first portion of the second interlayer insulating layer is disposed in the cell region and the second portion of the second interlayer insulating layer is disposed in the peripheral region;
• forming a second peripheral circuit wiring layer pattern on the second portion of the second insulating layer and forming a second contact passing through the second interlayer insulating layer so as to constitute the peripheral circuit;
• forming a mask pattern exposing the first portion of the second interlayer insulating layer with covering the second portion of the second interlayer insulating layer;
• selectively removing the exposed whole first portion of the second interlayer insulating layer with remaining the second portion of the second interlayer insulating layer,
• wherein a portion of the first insulating layer in the cell region is exposed by the remaining second portion of the second interlayer insulating layer;
• forming an etch stopper over the exposed portion of the first insulating layer with extending to cover the remaining second portion of the second interlayer insulating layer;
• forming a mold layer on the etch stopper;
• forming storage nodes that pass through a portion of the mold layer in the cell region;
• selectively removing the mold layer to expose the storage nodes while the etch stopper protects the second portion of the second interlayer insulating layer from the removing;
• forming a dielectric layer and a plate node, which cover the exposed storage nodes;
• forming a third interlayer insulating layer covering the plate node;
• and
• forming third contacts that pass through the third interlayer insulating layer so as to be connected to the plate node and the second peripheral circuit wiring layer pattern, respectively.