Floating body storage device employing a charge storage trench

A semiconductor structure comprising:

• a trench located in an upper portion of a dielectric material layer, said trench extending from a top surface of said dielectric material layer into said dielectric material layer to expose a sublayer of said dielectric material layer;
• a conductive material portion and dielectric material portions located in said trench, each of said dielectric material portions laterally contacting said conductive material portion and a sidewall of said trench;
• and
• a field effect transistor located on said top surface of said dielectric material layer, wherein a top surface of said conductive material portion is in physical contact with a body region of said field effect transistor,
• wherein said dielectric material layer comprises a dielectric material having an etch rate different from a dielectric material of said dielectric material portions.

A semiconductor structure comprising:

• a trench located in an upper portion of a first portion of a dielectric material layer, said trench extending from a top surface of said dielectric material layer into said dielectric material layer to expose a sublayer of said dielectric material layer;
• a plurality of conductive material portions and a plurality of dielectric material portions located in said trench, said plurality of dielectric material portions laterally separating said plurality conductive material portions from one another and contacting sidewalls of said trench;
• a plurality of first field effect transistors located on said first portion of said dielectric material layer, wherein a top surface of each of said plurality of conductive material portions is in physical contact with a body region of a corresponding one of said plurality of first field effect transistors;
• and
• a plurality of second field effect transistors present on a second portion of said dielectric material layer, wherein each of said plurality of second field effect transistors has a bottom surface contacting portions of said top surface located in said second portion of said dielectric material layer,
• wherein said dielectric material layer comprises a dielectric material having an etch rate different from a dielectric material of said plurality of dielectric material portions.