US 9,318,489 B2Granted

Complex circuits utilizing fin structures

AssigneeInternational Business Machines Corporation

InventorsKangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Kern Rim

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Abstract

A method of forming a semiconductor structure includes forming a multilayer lattice matched structure having an unstrained layer, a first strained layer, and a second strained layer formed between the unstrained and the first strained layer. A first opening in the multilayer structure is etched and a second strained fill material having a same material as the second strained layer is deposited. A second opening in the multilayer structure is etched and an unstrained fill material having a same material as the unstrained layer is deposited. A first strained fill material having a same material as the first strained layer is then deposited between the unstrained fill and the second strained fill. A second strained fin is formed from the deposited second strained fill material, a first strained fin is formed from the deposited first strained fill material, and an unstrained fin is formed from the deposited unstrained fill material.

Claims6

Dependent claims

A semiconductor structure comprising:

an unstrained substrate layer;
a dielectric layer located within a top surface region of the unstrained substrate layer;
a first strained fin structure located on the dielectric layer, the first strained fin structure having a first strain characteristic;
an unstrained fin structure located on the dielectric layer, the unstrained fin structure located adjacent to the first strained fin structure;
a second strained fin structure located on the dielectric layer between the first strained fin structure and the unstrained fin structure, the second strained fin structure having a second strain characteristic;
a third strained fin structure located on the dielectric layer adjacent to the first strained fin structure, the third strained fin structure having the second strain characteristic;
and
a fourth strained fin structure located on the dielectric layer adjacent to the at least one unstrained fin structure, the fourth fin structure having a second strain characteristic;
wherein the first strained fin structure, the second strained fin structure, the third strained fin structure, the fourth strained fin structure, and the unstrained fin structure are formed from a multilayer lattice matched structure.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/805,529Filed 22 Jul 2015 · division
Priority: 20 May 2014
Published: US 2015/0340291 A126 Nov 2015
Granted: 19 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification21 codes

H10D 84/834
Of only insulated-gate FETs [IGFET]: comprising FinFETs
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/62
Insulated-gate field-effect transistors [IGFET]: fin field-effect transistors [FinFET]
H10D 30/791
Insulated-gate field-effect transistors [IGFET]: arrangements for exerting mechanical stress on the crystal lattice of the channel regions

Family

Application14/282,050Parent of this division · filed 20 May 2014
US 2015/0340364 A1Pre-grant publication · published 26 Nov 2015
US 9,190,329 B1Parent of this division
US 2015/0340291 A1Published application
US 9,318,489 B2This patent

From the US filing history. Foreign family members aren’t listed.