Semiconductor integrated circuit devices

A semiconductor integrated circuit device comprising:

• a first active region on a surface of a substrate, wherein the first active region has a length in a first direction;
• a second active region on the surface of the substrate, wherein the second active region has a length in the first direction, and wherein the length of the second active region is greater than the length of the first active region;
• a first gate electrode that extends across the first active region in the first direction, wherein the first gate electrode has a length in the first direction;
• a second gate electrode that extends across, the second active region in the first direction wherein the second gate electrode has a length in the first direction that is greater than the length of the first gate electrode in the first direction wherein the first and second gate electrodes are parallel in the first direction, wherein the first and second gate electrode are spaced apart in a second direction and wherein the first and second directions are orthogonal;
• a first dummy gate pattern spaced apart from the first gate electrode;
• and
• a second dummy gate pattern spaced apart from the first gate electrode, wherein the first gate electrode is arranged between the first and second dummy gate patterns in the first direction,
• wherein a first axis in the first direction intersects the first gate electrode and the first and second dummy patterns, and
• wherein a second axis in a second direction intersects the first and second gate electrodes.

A. semiconductor integrated circuit device comprising:

• a first active region on a surface of a substrate;
• a second active region on the surface of the substrate;
• a field region on the surface of the substrate surrounding the first and second active regions;
• a first gate electrode that extends across the first active region in a first direction;
• a second gate electrode that extends across the second active region in the first direction;
• and
• a dummy gate pattern on the field region between the first and second active regions, wherein the dummy gate pattern extends across the field region in the first direction in parallel with the first and second gate electrodes, wherein an axis in a second direction intersects center points of the first gate electrode, the second gate electrode, and the dummy gate pattern.