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US 9,318,476 B2Granted
High performance standard cell with continuous oxide definition and characterized leakage current
AssigneeQUALCOMM Incorporated
InventorsXiangdong Chen, Ohsang Kwon, Foua Vang, Animesh Datta, Seid Hadi Rasouli
Life of this patent
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Abstract
A transistor cell is provided that includes a dummy gate overlaying a continuous oxide definition (OD) region. A first portion of the OD region adjacent a first side of the dummy forms the drain. The cell includes a local interconnect structure that couples the dummy gate and a portion of the OD region adjacent a second opposing side of the dummy gate to a source voltage.
Claims14
A cell comprising:
- a continuous oxide definition (OD) region defined in a substrate;
- a gate for a transistor between a first dummy gate and a second dummy gate, wherein a source for the transistor is defined in a first portion of the continuous OD region between the gate and the first dummy gate, and wherein a drain for the transistor is defined in a second portion of the continuous OD region between the gate and a first side of the second dummy gate;
- a first gate-directed local interconnect coupled to a third portion of the continuous OD region adjacent a second opposing side of the second dummy gate;
- a first diffusion-directed local interconnect configured to couple the first gate-directed local interconnect to the second dummy gate;
- and
- a first via configured to couple the first diffusion-directed local interconnect to a source voltage interconnect in a metal layer adjacent the substrate.
3 more elements
A method for forming a cell, comprising:
- forming a continuous oxide definition (OD) region defined in a substrate;
- forming a gate for a transistor arranged according to a gate pitch between a first dummy gate and a second dummy gate, wherein a source for the transistor is defined in a portion of the continuous OD region between the gate and the first dummy gate, and wherein a drain for the transistor is defined in a portion of the continuous OD region between the gate and a first side of the second dummy gate;
- forming a first gate-directed local interconnect coupled to a portion of the continuous OD region adjacent a second opposing side of the second dummy gate;
- forming a first diffusion-directed local interconnect configured to couple the first gate-directed local interconnect to the second dummy gate;
- and
- forming a via configured to couple the first gate-directed local interconnect to a source voltage supply.
3 more elements
Dependencies are inferred from the claim text.