3-D integrated semiconductor device comprising intermediate heat spreading capabilities

A semiconductor device, comprising:

• a first chip comprising a first chip area, a first heat spreading layer positioned directly on and covering said first chip area, and a first peripheral heat sink region laterally enclosing said first chip area and directly contacting said first heat spreading layer, wherein said first chip area comprises a first substrate, a first device layer positioned directly on and covering said first substrate and comprising a plurality of first transistor elements positioned proximate an active surface of said first chip area, and a first metallization system positioned directly on and covering said first device layer, said first peripheral heat sink region comprising a plurality of first thermal contact elements;
• and
• a second chip attached to said first chip, said second chip comprising a second chip area and a second peripheral heat sink region laterally enclosing said second chip area, wherein said second chip area comprises a second substrate, a second device layer positioned directly on and covering said second substrate and comprising a plurality of second transistor elements positioned proximate an active surface of said second chip area, and a second metallization system positioned directly on and covering said second device layer, and wherein said plurality of first thermal contact elements attach said first peripheral heat sink region of said first chip to said second peripheral heat sink region of said second chip and are adapted to conduct heat from said first peripheral heat sink region to said second peripheral heat sink region.

A semiconductor device, comprising:

• a first chip, comprising:
• a first chip area comprising a first substrate, a first device layer positioned above said first substrate, a first metallization system positioned above said first device layer, and a first heat spreading layer positioned above said first metallization system, said first device layer comprising a plurality of first circuit elements positioned proximate an active surface of said first chip area;
• a first peripheral heat sink region laterally enclosing said first chip area, wherein said first heat spreading layer laterally contacts said first peripheral heat sink region and is adapted to dissipate heat from said first chip area to said first peripheral heat sink region, said first peripheral heat sink region comprising a plurality of first thermal contact elements;
• and
• a plurality of second thermal contact elements positioned above said first heat spreading layer;
• and
• a second chip attached to said first chip, said second chip comprising:
• a second chip area comprising a second substrate, a second device layer positioned above said second substrate, a second metallization system positioned above said second device layer, and a first heat spreading layer positioned above said first metallization system, said second device layer comprising a plurality of second circuit elements positioned proximate an active surface of said second chip area;
• a plurality of third thermal contact elements positioned below said second substrate;
• and
• a second peripheral heat sink region laterally enclosing said second chip area, wherein said second heat spreading layer laterally contacts said second peripheral heat sink region and is adapted to dissipate heat from said second chip area to said second peripheral heat sink region, wherein said plurality of first thermal contact elements attach said first peripheral heat sink region of said first chip to said second peripheral heat sink region of said second chip and are adapted to conduct heat from said first peripheral heat sink region to said second peripheral heat sink region, and wherein each of said plurality of second thermal contact elements is attached to a corresponding one of said plurality of third thermal contact elements and is adapted to conduct heat from said first chip to said second chip.