Wafer level array of chips and method thereof

A wafer level array of chips, comprising:

• a semiconductor wafer having at least two adjacent chips and a carrier layer, each chip having an upper surface and a lower surface, the chip having at least one device on the upper surface, and the carrier layer covering the upper surface of each chip;
• and
• at least one extending-line protection disposed below the carrier layer and between the chips, and a thickness of the extending-line protection is less than that of the chip,
• wherein the extending-line protection has at least one extending-line, wherein the extending line is electrically conductive.

A chip package, comprising:

• a carrier layer having an active area and a periphery area surrounding the active area;
• a semiconductor chip disposed in the active area and below the carrier layer, the semiconductor having an upper surface and a lower surface, the semiconductor having at least one device dispose on the upper surface and covered by the carrier layer, and at least one connecting pad structure electrically connected to the device;
• a plurality of vias, the vias extending from the lower surface to the upper surface, the vias contacting the connecting pad structure and exposing a part of the connecting pad structure;
• an isolation layer extending from the lower surface to the upper surface, and a part of the isolation layer disposed in the vias;
• a conducting layer disposed below the isolation layer and extending from the lower surface to the upper surface, a part of the conducting layer disposed in the vias, wherein the part of the conducting layer is electrically connected to the device through the connecting pad structure;
• a packaging layer disposed below the conducting layer;
• at least one extending-line protection corresponding to the periphery area and disposed below the carrier layer;
• and
• at least one extending-line disposed in the extending-line protection, wherein the extending-line is electrically conductive.