Self-alignment structure for wafer level chip scale package

A method, comprising:

• depositing a metal layer over a semiconductor substrate;
• patterning the metal layer to form a metal pad and a metal base on the semiconductor substrate;
• forming a passivation layer over the semiconductor substrate, the metal base and the metal pad;
• forming a polymer insulating layer over the passivation layer, the metal pad and the metal base;
• forming a first opening passing through the polymer insulating layer and the passivation layer to expose a portion of the metal pad;
• depositing a copper-containing layer over the polymer insulating layer;
• patterning the copper-containing layer to form a support structure with a second opening and a post-passivation interconnect (PPI) line through the second opening,
• wherein patterning the copper-containing layer forms the support structure of which a top is elevated higher than a top of the PPI line by a thickness of the metal pad;
• and
• forming a conductive bump on the support structure.