Method of forming a plurality of bumps on a substrate and method of forming a chip package
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsJing-Cheng Lin, Po-Hao Tsai
Life of this patent
Estimating the term…
Abstract
A method of forming a plurality of bump structures on a substrate includes forming an under bump metallurgy (UBM) layer on the substrate, wherein the UBM layer contacts metal pads on the substrate. The method further includes forming a photoresist layer over the UBM layer, wherein the photoresist layer defines openings for forming the plurality of bump structures. The method further includes plating a plurality of layers in the openings, wherein the metal layers are part of the plurality of bump structures. The method further includes planarizing the plurality of bump structures after the metal layers are plated to a targeted height from a surface of the substrate.
Claims20
A method of forming a plurality of bump structures on a substrate, comprising:
- forming an under bump metallurgy (UBM) layer on the substrate, wherein the UBM layer contacts metal pads on the substrate;
- forming a photoresist layer over the UBM layer, wherein the photoresist layer defines openings for forming the plurality of bump structures;
- plating a plurality of layers in each opening of the openings, wherein the layers are part of the plurality of bump structures, wherein a height of the plurality of layers in a corresponding opening of the openings varies from a center of the substrate to an edge of the substrate;
- and
- planarizing the plurality of bump structures after the layers are plated to a targeted height from a surface of the substrate.
A method of forming a chip package, comprising:
- providing a first chip with a first plurality of bump structures, wherein the first plurality of bump structures are planarized to a first height;
- providing a substrate with a second plurality of bump structures, wherein the second plurality of bump structures are planarized to a second height;
- and
- bonding the first and second plurality of bump structures together, wherein a standoff distance exists between the first chip and the substrate, and a thickness of a solder layer between a bump structure of the first plurality of bump structures to a corresponding bump structure of the second plurality of bump structures varies across the chip package.
A method of forming a chip package, the method comprising:
- forming a plurality of bump structures on a first chip, wherein forming the plurality of bump structures comprises:
- forming a solder layer in each bump structure of the plurality of bump structures, wherein a solder layer in a first bump structure of the plurality of bump structures near a center of the first chip is thicker than a solder layer in a second bump structure of the plurality of bump structures near an edge of the first chip, and a solder layer in a third bump structure of the plurality of bump structures positioned between the first bump structure and the second bump structure is thicker than the solder layer of the second bump structure and thinner than a solder layer of the first bump structure.
Dependencies are inferred from the claim text.