Packaged semiconductor device, a semiconductor device and a method of manufacturing a packaged semiconductor device

A packaged semiconductor device comprising a package and a semiconductor device, the semiconductor device comprising:

• a first GND-pad and a second GND-pad bonded to one or more GND-pins of the package with a first bond wire and a second bond wire respectively;
• a first functional pad bonded to a first functional pin of the package with a third bond wire;
• a semiconductor layer of a P-type conductivity;
• a first semiconductor component formed in the semiconductor layer, the first semiconductor component comprising a first P-type region and a first N-type region, the first functional pad being in contact with the first P-type region, the first N-type region isolating the first P-type region from the semiconductor layer, and the first semiconductor component being arranged to, when a transient current is applied to the first functional pin, divert at least part of the transient current applied to the first functional pin to the first GND-pad from the first P-region to the first GND-pad via at least a first PN-junction;
• a second semiconductor component formed in the semiconductor layer, the second semiconductor component comprising a second N-type region of a terminal of the second semiconductor component associated with the first functional pad;
• a second P-type region formed in the semiconductor layer, the first GND-pad being in contact with the second P-type region, the second P-type region being isolated from first N-type region of the first semiconductor component;
• a third N-type region formed in the semiconductor layer, the second GND-pad being in contact with the third N-type region, the third N-type region being isolated from the first semiconductor component, the second semiconductor component and the second P-type region;
• at least part of the second P-type region being arranged in between the first semiconductor component and the second semiconductor component;
• and
• at least part of the third N-type region being arranged in between the at least part of the first P-type region and the second semiconductor component.