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AssigneeSemiconductor Manufacturing International (Beijing) Corporation
InventorsXinpeng Wang, Yi Huang, Shih-Mou Chang
Estimating the term…
A semiconductor device and a manufacturing method thereof is provided. The method comprises: providing a substrate for the semiconductor device with a gate structure and a first dielectric interlayer being formed thereon, said gate structure comprising a metal gate and an upper surface of said first dielectric interlayer being substantially flush with an upper surface of said gate; forming an interface layer to cover at least the upper surface of said gate such that the upper surface of said gate is protected from being oxidized; and forming a second dielectric interlayer on said interface layer.
A semiconductor device, comprising:
Dependencies are inferred from the claim text.
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From the US filing history. Foreign family members aren’t listed.
No references of this kind are recorded.
Arrangements for protection of devices
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
Manufacture or treatment: of dielectric parts thereof
By forming openings in the dielectric parts: using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
About 5 years 1 month of term left · ends 9 Dec 2031 (estimated)
The present invention relates to the field of semiconductor fabrication techniques, and more specifically, relates to semiconductor devices and manufacturing methods therefor.
As known by those of ordinary skill in the art, there is a gate-last approach and a gate-first approach for manufacturing a semiconductor device such as a field-effect transistor.
In the gate-last approach, referring to FIG. 8, a dielectric layer 807 and a dummy gate are formed on a substrate 809, preferably, a lightly doped region (LDD) implantation of the substrate 809 is carried out, and then one or more spacers 803 are formed; after the formation of such a dummy gate as described above, source and drain implantation is carried out; and then a first dielectric interlayer 805 is formed and is chemical mechanical polished (CMP) so as to substantially expose an upper surface of the dummy gate; the dummy gate is then removed; and then, a gate dielectric layer and a metal gate are formed, for example, by depositing gate dielectric (in some embodiments, it may be a high-k dielectric) and metal gate material, followed by the CMP process so as to form a gate 801; thereafter, the gate is re-coated with an dielectric interlayer; and then one or more contact holes are subsequently formed.
The accompanying drawings, which are incorporated herein together with the description serve to explain the principles of the invention. The present invention can be better understood through reading the following detailed description of embodiments with reference to the attached drawings, in which:
FIGS. 1-7 are diagrams showing various stages in a method of manufacturing a semiconductor device according to an embodiment of the present invention; and
FIG. 8 is a semiconductor device made by a prior art manufacturing process.
It is understood that these drawings are merely illustrative in nature and are not intended to limit the scope of the present invention. In the drawings, various components are not illustrated strictly to or according to their actual shapes, wherein, some of the components (such as, layers or parts) may be enlarged relative to others to more clearly illustrate the principles of the present invention. Moreover, details that may obscure the gist of the present invention are not shown in the drawings.
The embodiments of the present invention will be described below in conjunction with the drawings.
FIGS. 1-7 show steps in a method of manufacturing a semiconductor device according to an embodiment of the present invention.