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US 9,318,444 B2Granted
Structure designs and methods for integrated circuit alignment
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorHsien-Wei Chen
Life of this patent
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Abstract
Devices and methods for pattern alignment are disclosed. The device includes an assembly isolation region, a seal ring region around the assembly isolation region, and a scribe line region around the seal ring region, and a plurality of die alignment marks disposed within the seal ring region that are alternately disposed adjacent the scribe line region and the assembly isolation region.
Claims20
A semiconductor device, comprising:
- a die including an assembly isolation region, a seal ring region around the assembly isolation region, and a scribe line region around the seal ring region;
- and
- a plurality of die alignment marks disposed within the seal ring region that are alternately disposed adjacent the scribe line region and the assembly isolation region.
A semiconductor device, comprising:
- a die comprising an integrated circuit region, an assembly isolation region around the integrated circuit region, and a seal ring region around the assembly isolation region;
- and
- a die alignment mark within the seal ring region or the assembly isolation region of the die, wherein the die alignment mark includes overlay marks formed in an active (OD) layer, a polysilicon (POLY) layer, and a contact (CO) layer.
A method, comprising:
- providing a semiconductor device;
- defining a die area on the semiconductor device, wherein the die area includes a seal ring region;
- and
- forming a plurality of die alignment marks within the seal ring region, wherein the plurality of die alignment marks are alternately disposed adjacent an outer edge of the seal ring region and an inner edge of the seal ring region.
1 more element
Dependencies are inferred from the claim text.