Integrated circuit having a MOM capacitor and method of making same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsChi-Wen Liu, Chao-Hsiung Wang
Life of this patent
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Abstract
An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
Claims19
A method of forming an integrated circuit comprising:
- forming on a substrate a dielectric layer having a first semiconductor fin therein and a second semiconductor fin therein;
- removing a top portion of the first semiconductor fin to form a first recess in the dielectric layer and removing a top portion of the second semiconductor fin to form a second recess in the dielectric layer;
- and
- forming a first electrode in the first recess above the first semiconductor fin and a second electrode physically isolated from the first electrode in the second recess above the second semiconductor fin, the first electrode and the second electrode comprising electrodes of a MOM capacitor, wherein no portions of the first electrode and the second electrode are disposed on sidewalls of the first semiconductor fin and the second semiconductor fin.
A method of forming an integrated circuit comprising:
- forming a MOM capacitor having a first electrode formed atop a first semiconductor fin, a second electrode formed atop a second semiconductor fin, and a capacitor dielectric interjacent the first and second semiconductor fins, wherein a surface of the first electrode facing away from the first semiconductor fin and a surface of the second electrode facing away from the second semiconductor fin are coplanar with or at a level below a surface of the capacitor dielectric facing away from the first and second semiconductor fins;
- and
- forming a finFET device having source and drain regions formed in a third semiconductor fin, wherein the third semiconductor fin is formed simultaneously with the first and second semiconductor fins.
A method of forming an integrated circuit comprising:
- forming a first fin and a second fin on a semiconductor substrate;
- forming a dielectric on the semiconductor substrate, wherein the dielectric has a substantially planar top surface and surrounds the first fin and second fin, respectively, on at least two sides of the first fin and second fin, respectively,
- recessing the first fin and the second fin to have a top surface, respectively, below the top surface of the dielectric, thus forming a first recess and a second recess;
- partially filling the first recess and second recess, respectively, with a liner, thus forming a third recess and a fourth recess;
- and
- forming a first capacitor electrode in the third recess and a second capacitor electrode in the fourth recess, wherein no portion of the first capacitor electrode is disposed outside the third recess, and wherein no portion of the second capacitor electrode is disposed outside the fourth recess.
Dependencies are inferred from the claim text.