Flat no-lead package and the manufacturing method thereof
AssigneeChipMOS Technologies Inc.
InventorChi-Jin Shih
Life of this patent
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AssigneeChipMOS Technologies Inc.
InventorChi-Jin Shih
Estimating the term…
A flat no-lead package includes an encapsulating material, and a die pad, a chip, a plurality of first contact pads and a plurality of second contact pads disposed in the encapsulating material. The encapsulating material has a package bottom surface. The die pad has a plurality of die pad extensions extending from the edges thereof. The chip is mounted on the die pad. The first contact pads are disposed near the edges of the encapsulating material and electrically coupled to the chip. The second contact pads are located between the die pad and the first contact pads and electrically coupled to the chip. Each of the second contact pads have a second contact pad extension corresponding to one of the die pad extensions respectively. The bottom surfaces of the first contact pads, the second contact pads and the second contact pad extensions are exposed on the package bottom surface.
A flat no-lead package comprising:
A method for manufacturing a flat no-lead package, comprising:
Dependencies are inferred from the claim text.