Chip stack packages, system in packages including the same, and methods of operating the same

A stack package comprising:

• a plurality of semiconductor chips in a first channel group and a plurality of semiconductor chips in a second channel group, the plurality of semiconductor chips in the second channel group stacked on the plurality of semiconductor chips in the first channel group and the plurality of semiconductor chips in the first channel group stacked on a package substrate,
• wherein each of the plurality of semiconductor chips in the first and second channel groups includes data I/O pads for transmitting data I/O signals, a flag pad, disposed on a semiconductor substrate of each, respective, semiconductor chip from the plurality of semiconductor chips, for receiving a flag signal, a chip enable pad for receiving a chip enable signal, and a buffer for controlling a switching operation between the data I/O pads and an internal circuit of the corresponding semiconductor chip,
• wherein the data I/O pads of one of the plurality of semiconductor chips in the first and second channel groups are electrically connected to the data I/O pads of the other semiconductor chips through first wires, and the flag pads of the plurality of semiconductor chips in the first and second channel groups is electrically connected to each other through a second wire,
• wherein the chip enable pads of the plurality of semiconductor chips in the first channel group are electrically connected to respective ones of the chip enable pads of the plurality of semiconductor chips in the second channel group,
• wherein the package substrate includes a pad, the pad directly electrically connected, through the second wire, to a first channel flag pad of a first semiconductor chip included in the first channel group and stacked on the package substrate,
• wherein a second semiconductor chip, included in the first channel group, is stacked between the first semiconductor chip and a third semiconductor chip included in the second channel group, and includes a second channel flag pad, and
• wherein the second channel flag pad is directly electrically connected to the first channel flag pad of the first semiconductor chip through the second wire.

A stack package comprising:

• at least three channel groups stacked on a package substrate, a first channel group stacked on a second channel group, the second channel group stacked on a third channel group, and the third channel group stacked on the package substrate,
• wherein each of the at least three channel groups includes a plurality of semiconductor chips,
• wherein each of the plurality of semiconductor chips includes data I/O pads for transmitting data I/O signals, a flag pad, disposed on a semiconductor substrate of each, respective, semiconductor chip from the plurality of semiconductor chips, for receiving a flag signal, a chip enable pad for receiving a chip enable signal, and a buffer for controlling a switching operation between the data I/O pads and an internal circuit of the corresponding semiconductor chip,
• wherein the data I/O pads of one of the plurality of semiconductor chips are electrically connected to the data I/O pads of the other semiconductor chips through first wires, and the flag pads of the plurality of semiconductor chips in each of the at least three channel groups are electrically connected to each other through a second wire,
• wherein the chip enable pads in one of the at least three channel groups are electrically connected to respective ones of the chip enable pads in each of the other channel groups,
• wherein the package substrate includes a pad, the pad directly electrically connected, through the second wire, to a first channel flag pad of a first semiconductor chip included in the first channel group and stacked on the package substrate,
• wherein a second semiconductor chip, included in the first channel group, is stacked between the first semiconductor chip and a third semiconductor chip included in the second channel group, and includes a second channel flag pad, and
• wherein the second channel flag pad is directly electrically connected to the first channel flag pad of the first semiconductor chip through the second wire.