Semiconductor device and structure
AssigneeMonolithic 3D Inc.
InventorsZvi Or-Bach, Zeev Wurman
Life of this patent
Estimating the term…
Abstract
A 3D device, including: a first layer including first transistors, the first transistors interconnected by a first layer of interconnection; a second layer including second transistors, the second transistors overlaying the first layer of interconnection, where the first layer includes a first clock distribution structure, where the second layer includes a second clock distribution structure, where the second clock distribution structure is connected to the first clock distribution structure with a plurality of through layer vias, and where the second transistors are aligned to the first transistors with less than 100 nm alignment error.
Claims20
A 3D device, comprising:
- a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;
- a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,
- wherein said first layer comprises a first clock distribution structure,
- wherein said second layer comprises a second clock distribution structure,
- wherein said second clock distribution structure is connected to said first clock distribution structure with a plurality of through layer vias, and
- wherein said second transistors are aligned to said first transistors with less than 100 nm alignment error.
A 3D device, comprising:
- a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;
- a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,
- wherein said first layer comprises a plurality of first flip-flops connected to form a first scan chain,
- wherein said second layer comprises a plurality of second flip-flops connected to form a second scan chain, and
- wherein said second transistors are aligned to said first transistors with less than 100 nm alignment error.
A 3D device, comprising:
- a first layer comprising first transistors, said first transistors interconnected by a first layer of interconnection;
- a second layer comprising second transistors, said second transistors overlaying said first layer of interconnection,
- wherein said first layer comprises a first bus, said first bus interconnecting a plurality of first logic units,
- wherein said second layer comprises a second bus, said second bus interconnecting a plurality of second logic units,
- wherein said first bus and said second bus are interconnected,
- wherein said interconnected comprise through layer vias, and
- wherein said second transistors are aligned to said first transistors with less than 100 nm alignment error.
Dependencies are inferred from the claim text.