Stacked semiconductor chips including test circuitry

#The present invention relates to a semiconductor device in which a plurality of semiconductor integrated circuits are three-dimensionally integrated by using through silicon vias (TSV).

#Recently, in a semiconductor integrated circuit (LSI: Large Scale Integrated Circuit), the amount of the circuits integrated in one chip has been increased and the performance of the circuits has also been improved along with the further miniaturization in the semiconductor manufacturing processes. However, when chips are sealed in a package and the package is mounted on a board, communication performance is degraded due to the long communication distance between the chips, and the communication performance cannot catch up with the performance improvement in the chips. Moreover, due to the influence of, for example, miniaturization limit and increase in the cost to use most-advanced processes, the conventional performance improvement by the integration onto one chip will not always be the most optimum solution in the future.

#As a technique for improving the performance between chips, Patent Document 1 discloses the technique of three-dimensionally stacking a plurality of chips and connecting the respective chips by using through silicon vias to carry out inter-chip communication. Also, Patent Document 2 introduces the technique of finding out short-circuit fault of through electrodes used for signals.

#FIG. 1 is a schematic drawing of the disposition of TSVs of the stacked LSIs to which the present invention is applied;

#FIG. 2 is a cross-sectional view of the stacked LSIs to which the present invention is applied;

#FIG. 3 is a schematic drawing of the disposition of TSVs and circuits of the stacked LSIs to which the present invention is applied;

#FIG. 1 shows a schematic drawing of the disposition of through silicon vias (TSVs) of three-dimensionally stacked LSIs using the present invention. In FIG. 1, black circles represent power-supply TSVs for supplying power to stacked chips, and white circles represent signal-line TSVs which transmit signals between the stacked chips. The power-supply TSVs are disposed in a plurality of rows in an outer peripheral part of the chips, and the signal-line TSVs are disposed inside them. FIG. 2 shows the cross-sectional structure in which two CPU chips on which a plurality of CPUs (Central Processing Units) are mounted and two memory chips on which memory arrays are mounted are stacked by using this TSV disposing configuration. FIG. 2 is the cross section of the chips of FIG. 1 taken along the line A-A′. The power-supply TSVs and the signal-line TSVs connecting the respective chips are disposed at the same locations in the vertical direction. Each of the chips is stacked so that a metal wiring layer is directed downward, and the TSVs are connected to a metal wiring layer of the chip stacked thereabove, penetrate through a silicon layer of the chip stacked therebelow, and are connected to a metal wiring layer of the chip stacked therebelow. FIG. 7 shows this state. Here, the lowermost chip is connected to a package substrate. In this case, the metal wiring layer of the lowermost chip is directed downward in order to shorten the distance of the signal lines between the chip and the package substrate, and the metal wiring layers of all the stacked chips are directed downward in conformity to it.

#FIG. 3 shows an example of the disposition of TSVs and the disposition of CPUs in the CPU chip using the present invention. In this LSI chip, eight CPU cores CPU 1 to 8 are integrated. The TSVs for power supply and signal lines are disposed in the peripheral part of the chip, and the CPUs are disposed at a center part of the chip. In this manner, circuit blocks such as CPUs are disposed in the region in which the TSVs are not located.

#FIG. 4 shows an example of the disposition of TSVs and the disposition of memories in the memory chip using the present invention. The TSVs for power supply and signal lines are disposed in the peripheral part of the chip, and a RAM 1 and a RAM 2 serving as memory arrays are disposed at a center part of the chip. In this manner, circuit blocks such as memories are disposed in the region in which the TSVs are not located.