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US 9,318,390 B2Granted
CMOS circuit and method for fabricating the same
AssigneeSK hynix Inc.
InventorsKyong-Bong Rouh, Shang-Koon Na, Mi-Ri Lee, Hun-Sung Lee
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Abstract
A semiconductor device includes a semiconductor substrate and a gate insulation layer formed over the semiconductor substrate. A gate electrode is formed over the gate insulation layer. The gate electrode includes a silicon-containing electrode including a dopant, a capturing material to capture the dopant, and an activation control material to control an activation of the dopant.
Claims6
A method for fabricating a semiconductor device, the method comprising:
- forming a gate insulation layer over a semiconductor substrate;
- forming an undoped silicon-containing layer over the gate insulation layer;
- forming a doped silicon-containing layer by doping the undoped silicon-containing layer with a dopant;
- and
- forming a gate electrode by etching the doped silicon-containing layer,
- wherein the undoped silicon-containing layer includes a capturing material and an activation control material, wherein the capturing material includes carbon to capture the dopant, wherein activation control material includes germanium to control an activation of the dopant,
- wherein the undoped silicon-containing layer has a multi-layer structure, comprising:
- a first silicon-containing layer including the capturing material;
- and
- a second silicon-containing layer including the activation control material and stacked over the first silicon-containing layer,
- wherein the first silicon-containing layer does not include the activation control material.
8 more elements
A method for fabricating a CMOS circuit, the method comprising:
- forming a gate insulation layer over a semiconductor substrate having an NMOSFET region and a PMOSFET region;
- forming an undoped amorphous silicon layer over the gate insulation layer;
- forming a P-type doped amorphous silicon layer and an N-type doped amorphous silicon layer by doping the undoped amorphous silicon layer with a P-type dopant and an N-type dopant, respectively;
- forming gate structures by etching the P-type doped amorphous silicon layer and the N-type doped amorphous silicon layer;
- and
- annealing to activate the P-type dopant and the N-type dopant,
- wherein the undoped amorphous silicon layer contains a capturing material and an activation control material, wherein the capturing material includes carbon to capture the P-type dopant and the N-type dopant, wherein the activation control material includes germanium to control an activation of the P-type dopant and the N-type dopant,
- wherein the undoped amorphous silicon layer has a multi-layer structure, comprising:
- a first undoped amorphous silicon layer including the capturing material;
- and
- a second undoped amorphous silicon layer including the activation control material and stacked over the first undoped amorphous silicon layer.
- wherein the first undoped amorphous silicon layer does not include the activation control material.
9 more elements
Dependencies are inferred from the claim text.