Methods of forming substantially self-aligned isolation regions on FinFET semiconductor devices and the resulting devices

A method of forming a FinFET device comprising a channel region and a plurality of source/drain regions, the method comprising:

• forming a plurality of spaced-apart trenches that extend at least partially into a semiconductor substrate, said trenches defining a fin structure for said device comprised of a first semiconductor material positioned on said semiconductor substrate and a second semiconductor material positioned on said first semiconductor material, wherein said first semiconductor material is selectively etchable relative to said semiconductor substrate and said second semiconductor material and wherein said fin structure extends in a gate-length direction across what will become said channel region and said source/drain regions for said device;
• forming a patterned layer of insulating material above said fin structure, said patterned layer of insulating material having an opening at a location that corresponds approximately to a location of said channel region for said FinFET device;
• while masking portions of said fin structure with said patterned layer of insulating material, performing at least one selective isotropic etching process through said opening in said patterned layer of insulating material to selectively remove a portion of said first semiconductor material relative to said second semiconductor material and said substrate so as to thereby define a space between said second semiconductor material and said semiconductor substrate;
• filling substantially all of said space between said second semiconductor material and said semiconductor substrate with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become said channel region of said device;
• after filling substantially all of said space with said insulating material, forming a sacrificial gate structure within said opening in said patterned layer of insulating material;
• removing said patterned layer of insulating material;
• forming at least one sidewall spacer adjacent said sacrificial gate structure;
• forming a layer of insulating material adjacent said sidewall spacer;
• performing at least one etching process to remove said sacrificial gate structure to thereby define a gate cavity;
• and
• forming a final gate structure in said gate cavity.

A method of forming a FinFET device comprising a channel region and a plurality of source/drain regions, the method comprising:

• forming a patterned layer of insulating material above a fin structure comprised of an upper portion, a lower portion and an intermediate portion that is positioned vertically between said upper and lower portions of said fin structure, said patterned layer of insulating material having an opening at a location that corresponds approximately to a location of said channel region for said FinFET device;
• while masking portions of said fin structure with said patterned layer of insulating material, performing at least one selective etching process through said opening in said patterned layer of insulating material to selectively remove said intermediate portion of said fin structure relative to said upper and lower portions of said fin structure so as to thereby define a space between said upper and lower portions of said fin structure;
• filling substantially all of said space between said upper and lower portions of said fin structure with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become said channel region of said device;
• after filling substantially all of said space with said insulating material, forming a sacrificial gate structure within said opening in said patterned layer of insulating material;
• removing said patterned layer of insulating material;
• forming at least one sidewall spacer adjacent said sacrificial gate structure;
• forming a layer of insulating material adjacent said sidewall spacer;
• performing at least one etching process to remove said sacrificial gate structure to thereby define a gate cavity;
• and
• forming a final gate structure in said gate cavity.