US 9,318,384 B2Granted

Dielectric liner for a self-aligned contact via structure

AssigneeInternational Business Machines Corporation

InventorsVeeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz

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Abstract

At least one dielectric material layer having a top surface above the topmost surface of the gate electrode of a field effect transistor is formed. Active region contact via structures are formed through the at least one dielectric material layer to the source region and the drain region. A self-aligned gate contact cavity is formed over the gate electrode such that at least one sidewall of the gate contact cavity is a sidewall of the active region contact via structures. A dielectric spacer is formed at the periphery of the gate contact cavity by deposition of a dielectric liner and an anisotropic etch. A conductive material is deposited in the gate contact cavity and planarized to form a self-aligned gate contact via structure that is electrically isolated from the active region contact via structures by the dielectric spacer.

Claims15

Dependent claims

A semiconductor structure comprising:

a semiconductor material portion including a doped semiconductor region and located on a substrate;
a conductive material portion located above, and electrically insulated from said semiconductor material portion;
at least one dielectric material layer overlying said semiconductor material portion and said conductive material portion;
a first contact via structure extending through, and contacting, said at least one dielectric material layer and electrically shorted to said doped semiconductor region;
a second contact via structure extending through said at least one dielectric material layer and electrically shorted to said conductive material portion;
and
a dielectric spacer laterally surrounding said second contact via structure, wherein inner sidewalls of said dielectric spacer contact said sidewalls of said second contact via structure along an entire length of said sidewalls of said second contact via structure, and a bottom surface of said dielectric spacer is in contact with a top surface of said conductive material portion such that said dielectric spacer covers only an upper portion of lateral surfaces and said top surface of said conductive material portion.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/223,282Filed 24 Mar 2014
Published: US 2015/0270171 A124 Sep 2015
Granted: 19 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification13 codes

H10W 20/069
Of conductive parts of the interconnections: by forming self-aligned vias or self-aligned contact plugs
H10D 30/024
Of FETs having insulated gates [IGFET]: of fin field-effect transistors [FinFET]
H10D 30/0275
Of lateral single-gate IGFETs: forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised…
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]