US 9,318,377 B2Granted

Etch damage and ESL free dual damascene metal interconnect

AssigneeTaiwan Semiconductor Manufacutring Co., Ltd.

InventorsSunil Kumar Singh, Chung-Ju Lee, Tien-I Bao

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Abstract

A method of forming a dual damascene metal interconnect for a semiconductor device. The method includes forming a layer of low-k dielectric, forming vias through the low-k dielectric layer, depositing a sacrificial layer, forming trenches through the sacrificial layer, filling the vias and trenches with metal, removing the sacrificial layer, then depositing an extremely low-k dielectric layer to fill between the trenches. The method allows the formation of an extremely low-k dielectric layer for the second level of the dual damascene structure while avoiding damage to that layer by such processes as trench etching and trench metal deposition. The method has the additional advantage of avoiding an etch stop layer between the via level dielectric and the trench level dielectric.

Claims19

Dependent claims

A semiconductor device comprising a dual damascene metal interconnect structure, the dual damascene metal interconnect structure comprising:

a terminal;
a first layer overlying the terminal and comprising via openings in a field of a first dielectric, and excluding air gaps, wherein metal vias fill the via openings;
a first metal cap layer arranged in a lowermost portion of a via opening, the first metal cap layer having a lower portion making contact with the terminal and having an upper portion making contact with a metal via filling the via opening;
and
a second layer overlying the first layer and comprising metal bodies filling trenches in a field of a second dielectric, wherein the second dielectric includes air gaps that substantially reduce an effective dielectric constant of the second dielectric;
wherein the first and second dielectrics directly abut one another;
a second metal cap layer arranged over and abutting the metal bodies filling the trenches and having a metal composition which differs from that of the metal bodies and which differs from that of the first metal cap layer, wherein a lower surface of the second metal cap layer is at a height corresponding to the second dielectric and an upper surface of the second metal cap layer is co-planar with an upper surface of the second dielectric.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/146,941Filed 3 Jan 2014 · division
Priority: 19 Jun 2012
Published: US 2014/0117561 A11 May 2014
Granted: 19 Apr 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification19 codes

H10W 20/084
By forming openings in the dielectric parts: for dual-damascene structures
H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 20/057
By filling conductive material into holes, grooves or trenches: by selectively depositing, e.g. by using selective CVD or plating
H10W 20/063
Of conductive parts of the interconnections: by forming conductive members before forming protective insulating material

Family

Application13/526,640Parent of this division · filed 19 Jun 2012
US 2014/0117561 A1Pre-grant publication · published 1 May 2014
US 8,652,962 B2Parent of this division
US 2013/0334700 A1Published application
US 9,318,377 B2This patent

From the US filing history. Foreign family members aren’t listed.