Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
AssigneeGlobalfoundries Inc.
InventorsDouglas C. La Tulipe, Jr., Mark Todhunter Robson
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Abstract
A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
Claims11
A structure, comprising:
- a substrate;
- a dielectric etch stop layer in direct physical contact with a top surface of said substrate;
- a dielectric layer in direct physical contact with a top surface of said dielectric etch stop layer;
- a dielectric profile modulation layer in direct physical contact with a top surface of said dielectric layer, said dielectric layer between said dielectric etch stop layer and said dielectric profile modulation layer;
- an additional dielectric layer in direct physical contact with a top surface of said dielectric profile modulation layer;
- wherein said dielectric etch stop layer and said dielectric profile modulation layer each independently have respective thicknesses at least five times less than either a thickness of said dielectric layer or a thickness of said additional dielectric layer;
- and wherein a total thickness of said dielectric etch stop layer, said dielectric layer, said dielectric profile modulation layer and said additional dielectric layer is greater than or equal to about 1 micron;
- an opening having an upper region and an abutting lower region, said upper region extending from a top surface of said additional dielectric layer to said top surface of said profile modulation layer, said lower region extending from said top surface of said dielectric profile modulation layer to said top surface of said substrate;
- a first width of said opening measured in first direction parallel to said top surface of said dielectric layer at said top surface of said additional dielectric layer is greater than a second width of said opening measured in said first direction at said top surface of said profile modulation layer and greater than a third width of said opening measured in said first direction at said top surface of said substrate, said second width greater than or equal to said third width;
- a ratio of a depth of said opening measured in a second direction perpendicular to said first direction from said top surface of said additional dielectric layer to said top surface of said substrate to said third width is equal to or greater than five;
- and
- an electrical conductor completely filling said opening.
Dependencies are inferred from the claim text.