Semiconductor storage device comprising peripheral circuit, Shielding layer, and memory cell array
AssigneeSemiconductor Energy Laboratory Co., Ltd.
InventorsTomoaki Atsumi, Takashi Okuda
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Abstract
Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.
Claims20
A semiconductor storage device comprising:
- a peripheral circuit;
- a conductive film over the peripheral circuit;
- and
- a memory cell array over the conductive film,
- wherein the memory cell array comprises a memory cell comprising a transistor, and
- wherein entirety of the memory cell array overlaps with the conductive film.
A semiconductor storage device comprising:
- a peripheral circuit;
- a shielding layer over the peripheral circuit;
- and
- a memory cell array over the shielding layer,
- wherein the memory cell array comprises a memory cell comprising a transistor,
- wherein the shielding layer is configured to shield the peripheral circuit and the memory cell array from radiation noise generated between the peripheral circuit and the memory cell array, and
- wherein the shielding layer is configured to be supplied with a ground potential.
A semiconductor storage device comprising:
- a peripheral circuit;
- a first insulating film over the peripheral circuit;
- a conductive film over the first insulating film;
- a second insulating film over the conductive film;
- and
- a memory cell array over the second insulating film,
- wherein the memory cell array comprises a memory cell comprising a transistor electrically connected to an electrode,
- wherein a capacitor is formed using a region of the conductive film as a first electrode, a region of the second insulating film over the region of the conductive film, and a region of the electrode over the region of the second insulating film as a second electrode, and
- wherein entirety of the memory cell array overlaps with the conductive film.
Dependencies are inferred from the claim text.