Method of stressing a semiconductor layer
AssigneesSTMicroelectronics S.r.l., STMicroelectronics (Crolles 2) SAS
InventorsOlivier Nier, Denis Rideau, Pierre Morin, Emmanuel Josse
Life of this patent
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Abstract
One or more embodiments of the disclosure concerns a method of forming a stressed semiconductor layer involving: forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer, at least two first trenches in a first direction; introducing, via the at least two first trenches, a stress in the semiconductor layer and temporally decreasing, by annealing, the viscosity of the insulator layer; and extending the depth of the at least two first trenches to form first isolation trenches in the first direction delimiting a first dimension of at least one transistor to be formed in the semiconductor structure.
Claims26
A method of forming a stressed semiconductor layer, the method comprising:
- forming, in a surface of a semiconductor structure having a semiconductor layer in contact with an insulator layer having a viscosity, at least two first trenches having a first depth in a first direction;
- introducing, through said at least two first trenches, a stress in said semiconductor layer and temporarily decreasing, by annealing, the viscosity of said insulator layer;
- and
- forming in said first direction first isolation trenches delimiting a first dimension of at least one transistor to be formed in said semiconductor structure by extending said at least two first trenches from a first depth to a second depth.
A method comprising:
- in a semiconductor structure that includes a semiconductor layer located on an insulator layer having a viscosity, forming a plurality of trenches having a first depth in a first direction;
- introducing a material in the plurality of trenches;
- stressing the semiconductor layer and temporarily decreasing the viscosity of the insulator layer by annealing the semiconductor structure;
- and
- after annealing, forming first isolation trenches in the first direction for delimiting in a first dimension a transistor to be formed in the semiconductor structure by extending the two trenches from a first depth to a second depth, the second depth being deeper than the first depth.
A method comprising:
- in a semiconductor structure that includes a semiconductor layer located on an insulator layer having a viscosity, forming a plurality of trenches having a first depth in a first direction;
- introducing a material in the plurality of trenches;
- stressing the semiconductor layer and temporarily decreasing the viscosity of the insulator layer by annealing the semiconductor structure;
- after annealing the semiconductor structure, forming first isolation trenches in the first direction for delimiting in a first dimension a transistor to be formed in the semiconductor structure by extending the two trenches from a first depth to a second depth, the second depth being deeper than the first depth;
- and
- forming the transistor in the semiconductor structure.
Dependencies are inferred from the claim text.