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US 9,318,345 B2Granted
Enhancing transistor performance by reducing exposure to oxygen plasma in a dual stress liner approach
AssigneeGlobalfoundries Inc.
InventorsRonald Naumann, Volker Grimm, Andrey Zakharov, Ralf Richter
Life of this patent
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Abstract
When forming strain-inducing dielectric material layers above transistors of different conductivity type, the patterning of at least one strain-inducing dielectric material may be accomplished on the basis of a process sequence in which a negative influence of a fluorine species in an oxygen plasma upon removing the resist mask is avoided or at least significantly suppressed. For example, a substantially oxygen-free plasma process may be applied for removing the resist material.
Claims24
A method, comprising:
- forming a first strain-inducing dielectric layer above a first transistor and a second transistor of a semiconductor device;
- selectively removing a portion of said first strain-inducing layer from above said second transistor by covering said first transistor with a resist mask and performing a first plasma assisted etch process in a first processing chamber using a first process environment;
- moving said semiconductor device from said first processing chamber to a second processing chamber;
- removing said resist mask by performing a second plasma assisted process in said second processing chamber using a second process environment that is different from said first process environment;
- forming a second strain-inducing dielectric layer above said first transistor and said second transistor;
- selectively removing said second strain-inducing dielectric layer from above said first transistor in a third process environment by using a resist mask formed above said second transistor;
- and
- removing said resist mask in a fourth process environment that is different from said first and third process environments.
5 more elements
A method, comprising:
- forming a first strain-inducing dielectric layer above a first transistor and a second transistor;
- forming a resist mask above said first transistor so as to expose a portion of said first strain-inducing dielectric layer selectively above said second transistor;
- removing said exposed portion of said first strain-inducing dielectric layer in a first plasma ambient in the presence of said resist mask, wherein said first plasma ambient is established in a first process environment;
- and
- removing said resist mask in a second plasma ambient without supplying oxygen gas to said second plasma ambient, wherein said second plasma ambient is established in a second process environment that differs from said first process environment.
2 more elements
A method, comprising:
- forming a first transistor in and above a first active region;
- forming a second transistor in and above a second active region, said second active region comprising a strain-inducing semiconductor alloy;
- forming a strain-inducing layer above said first and second transistors;
- forming a resist mask so as to cover said strain-inducing layer above said first transistor and expose said strain-inducing layer above said second transistor;
- removing an exposed portion of said strain-inducing layer in a first process chamber by using a first plasma ambient based on fluorine radicals;
- and
- removing said resist mask in a second process chamber by using a second plasma ambient that is established so as to have a reduced fluorine and oxygen concentration compared to said first plasma ambient.
4 more elements
A method, comprising:
- forming a first strain-inducing dielectric layer above a first transistor and a second transistor;
- selectively removing a portion of said first strain-inducing layer from above said second transistor by covering said first transistor with a first resist mask and performing a first plasma assisted etch process in a first process environment;
- removing said first resist mask by performing a second plasma assisted process in a second process environment that is different from said first process environment;
- forming a second strain-inducing dielectric layer above said first transistor and said second transistor, wherein said second strain-inducing dielectric layer induces a different type of strain compared to said first strain-inducing dielectric layer;
- selectively removing said second strain-inducing dielectric layer from above said first transistor in a third process environment by using a second resist mask formed above said second transistor;
- and
- removing said second resist mask in a fourth process environment that is different from said first and third process environments.
4 more elements
A method, comprising:
- forming a first strain-inducing dielectric layer above a first transistor and a second transistor;
- forming a resist mask above said first transistor so as to expose a portion of said first strain-inducing dielectric layer selectively above said second transistor;
- establishing a first plasma ambient in a process environment;
- removing said exposed portion of said first strain-inducing dielectric layer in said first plasma ambient established in said process environment in the presence of said resist mask;
- establishing a second plasma ambient in said process environment substantially without generating a bias voltage;
- and
- removing said resist mask in said second plasma ambient established in said process environment without supplying oxygen gas to said second plasma ambient.
4 more elements
Dependencies are inferred from the claim text.