Non-volatile memory structure employing high-k gate dielectric and metal gate
AssigneeGlobalfoundries U.S. 2 LLC
InventorsNicolas Breil, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon
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AssigneeGlobalfoundries U.S. 2 LLC
InventorsNicolas Breil, Michael P. Chudzik, Rishikesh Krishnan, Siddarth A. Krishnan, Unoh Kwon
Estimating the term…
A high dielectric constant (high-k) gate dielectric for a field effect transistor (FET) and a high-k tunnel dielectric for a non-volatile random access memory (NVRAM) device are simultaneously formed on a semiconductor substrate. A stack of at least one conductive material layer, a control gate dielectric layer, and a disposable material layer is subsequently deposited and lithographically patterned. A planarization dielectric layer is deposited and patterned, and disposable material portions are removed. A remaining portion of the control gate dielectric layer is preserved in the NVRAM device region, but is removed in the FET region. A conductive material is deposited in gate cavities to provide a control gate for the NVRAM device and a gate portion for the FET. Alternately, the control gate dielectric layer may replaced with a high-k control gate dielectric in the NVRAM device region.
A semiconductor structure comprising a field effect transistor, said field effect transistor including:
A semiconductor structure comprising a field effect transistor, said field effect transistor including:
Dependencies are inferred from the claim text.