Methods of forming vertical cell semiconductor devices with single-crystalline channel structures
AssigneeSamsung Electronics Co., Ltd.
InventorsKanamori Kohji, Young-Woo Park, Jin-Taek Park, Jae-Duk Lee
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Abstract
Methods of fabricating a vertical cell semiconductor device including forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate, forming an amorphous silicon layer conforming to an inner wall of the hole, forming a silicon region on the amorphous silicon layer, and metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole.
Claims16
A method of fabricating a semiconductor device, the method comprising:
- forming alternating interlayer insulating layers and sacrificial layers on a substrate;
- forming a first capping layer on the interlayer insulating layers and the sacrificial layers;
- forming a channel hole passing through the first capping layer, the interlayer insulating layers and the sacrificial layers to expose a first portion of the substrate;
- forming a dielectric pattern conforming to a wall of the channel hole;
- forming an amorphous channel active pattern conforming to the dielectric pattern and the exposed first portion of the substrate;
- forming a channel core pattern in a space defined by the amorphous channel active pattern;
- forming an amorphous silicon layer on the first capping layer and the amorphous channel active pattern;
- forming a mask pattern on the amorphous silicon layer and the amorphous channel active pattern;
- forming an insulating barrier layer on the mask pattern;
- forming a metal catalytic layer on the insulating barrier layer;
- and
- annealing to change the amorphous silicon layer and the amorphous channel active pattern into a single-crystalline silicon layer and a single-crystalline channel active pattern, respectively.
A method of fabricating a semiconductor device, the method comprising:
- forming a stacked structure of alternating interlayer insulating layers and sacrificial layers on a substrate;
- forming a channel hole vertically passing through the stacked structure and exposing a portion of the substrate;
- forming a channel structure including amorphous silicon in the channel hole;
- forming an amorphous silicon region on the channel structure;
- forming a metal catalytic layer on the amorphous silicon region;
- annealing to change the amorphous silicon and the channel structure to single-crystalline silicon using a metal induced crystallization that proceeds from the amorphous silicon region to the channel structure;
- removing the metal catalytic layer;
- removing the crystallized silicon region prior to forming the bit line plug and the bit line;
- and
- forming a bit line plug and a bit line on the channel structure after removing the crystallized silicon region.
A method of fabricating a semiconductor device, the method comprising:
- forming a hole passing through a stacked structure of alternating insulating and sacrificial layers on a substrate;
- forming an amorphous silicon layer conforming to an inner wall of the hole;
- forming a silicon region on the amorphous silicon layer;
- metal induced crystallizing the amorphous silicon layer via the silicon region to form a single-crystalline channel structure in the hole;
- removing the silicon region;
- removing portions of the sacrificial layers to form word line spaces;
- forming word lines in the word line spaces;
- and
- forming a bit line electrically coupled to the channel structure.
Dependencies are inferred from the claim text.